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4c884f4ac3
Lowering certain float vectors without legal vector types could cause a crash due to a bad interaction between passing floats via GPRs and argument splitting. Split vector floats appear just like scalar floats. Under certain situations we choose to pass these float arguments via GPRs and use an XLenVT location and set the 'BCvt' info to track how they must be converted back to floating-point values. However, later logic for handling split arguments may take over, in which case we lose the previous information and set the 'Indirect' info, thus incorrectly lowering to integer types. I don't believe that we would have come across the notion of split floating-point arguments before. This patch addresses the issue by updating the lowering so that split arguments are only passed indirectly when they are scalar integer types. This has some change to how we lower some larger illegal float vectors, as can be seen in 'fastcc-float.ll' where the vector is now passed partly in registers and partly on the stack. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D102852
64 lines
2.0 KiB
LLVM
64 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64LP64F %s
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define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) {
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; RV64-LABEL: callee_v2f32:
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; RV64: # %bb.0:
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; RV64-NEXT: fmv.w.x ft0, a2
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; RV64-NEXT: fmv.w.x ft1, a0
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; RV64-NEXT: fmv.w.x ft2, a3
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; RV64-NEXT: fmv.w.x ft3, a1
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; RV64-NEXT: fadd.s ft2, ft3, ft2
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; RV64-NEXT: fadd.s ft0, ft1, ft0
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; RV64-NEXT: fmv.x.w a0, ft0
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; RV64-NEXT: fmv.x.w a1, ft2
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; RV64-NEXT: ret
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;
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; RV64LP64F-LABEL: callee_v2f32:
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; RV64LP64F: # %bb.0:
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; RV64LP64F-NEXT: fadd.s fa0, fa0, fa2
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; RV64LP64F-NEXT: fadd.s fa1, fa1, fa3
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; RV64LP64F-NEXT: ret
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%z = fadd <2 x float> %x, %y
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ret <2 x float> %z
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}
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define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) {
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; RV64-LABEL: callee_v4f32:
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; RV64: # %bb.0:
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; RV64-NEXT: fmv.w.x ft0, a4
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; RV64-NEXT: fmv.w.x ft1, a7
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; RV64-NEXT: fmv.w.x ft2, a3
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; RV64-NEXT: fmv.w.x ft3, a6
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; RV64-NEXT: fmv.w.x ft4, a2
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; RV64-NEXT: fmv.w.x ft5, a5
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; RV64-NEXT: fmv.w.x ft6, a1
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; RV64-NEXT: flw ft7, 0(sp)
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; RV64-NEXT: fadd.s ft5, ft6, ft5
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; RV64-NEXT: fadd.s ft3, ft4, ft3
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; RV64-NEXT: fadd.s ft1, ft2, ft1
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; RV64-NEXT: fadd.s ft0, ft0, ft7
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; RV64-NEXT: fsw ft0, 12(a0)
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; RV64-NEXT: fsw ft1, 8(a0)
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; RV64-NEXT: fsw ft3, 4(a0)
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; RV64-NEXT: fsw ft5, 0(a0)
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; RV64-NEXT: ret
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;
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; RV64LP64F-LABEL: callee_v4f32:
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; RV64LP64F: # %bb.0:
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; RV64LP64F-NEXT: fadd.s ft0, fa0, fa4
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; RV64LP64F-NEXT: fadd.s ft1, fa1, fa5
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; RV64LP64F-NEXT: fadd.s ft2, fa2, fa6
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; RV64LP64F-NEXT: fadd.s ft3, fa3, fa7
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; RV64LP64F-NEXT: fsw ft3, 12(a0)
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; RV64LP64F-NEXT: fsw ft2, 8(a0)
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; RV64LP64F-NEXT: fsw ft1, 4(a0)
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; RV64LP64F-NEXT: fsw ft0, 0(a0)
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; RV64LP64F-NEXT: ret
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%z = fadd <4 x float> %x, %y
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ret <4 x float> %z
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}
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