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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-30 07:22:55 +01:00
llvm-mirror/lib/Target/ARM
Evan Cheng 98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.

llvm-svn: 31947
2006-11-27 23:37:22 +00:00
..
.cvsignore Ignore generated files 2006-05-27 01:23:30 +00:00
ARM.h move ARMCondCodeToString to ARMAsmPrinter.cpp 2006-11-02 15:00:02 +00:00
ARM.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
ARMAsmPrinter.cpp implement load effective address similar to the alpha backend 2006-11-09 13:58:55 +00:00
ARMFrameInfo.h use @ for comments 2006-08-25 17:55:16 +00:00
ARMInstrInfo.cpp Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 2006-11-27 23:37:22 +00:00
ARMInstrInfo.h implement uncond branch insertion, mark branches with isBranch. 2006-10-24 16:47:57 +00:00
ARMInstrInfo.td implement load effective address similar to the alpha backend 2006-11-09 13:58:55 +00:00
ARMISelDAGToDAG.cpp implement load effective address similar to the alpha backend 2006-11-09 13:58:55 +00:00
ARMMul.cpp Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 2006-11-27 23:37:22 +00:00
ARMRegisterInfo.cpp Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 2006-11-27 23:37:22 +00:00
ARMRegisterInfo.h Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 2006-11-27 23:37:22 +00:00
ARMRegisterInfo.td initial support for frame pointers 2006-10-26 13:31:26 +00:00
ARMTargetAsmInfo.cpp Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
ARMTargetAsmInfo.h Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
ARMTargetMachine.cpp revert previous patch 2006-11-03 03:08:28 +00:00
ARMTargetMachine.h Implement a MachineFunctionPass to fix the mul instruction 2006-09-19 15:49:25 +00:00
Makefile added a skeleton of the ARM backend 2006-05-14 22:18:28 +00:00
README.txt add FSTD and FSTS 2006-10-17 13:36:07 +00:00

//===---------------------------------------------------------------------===//
// Random ideas for the ARM backend.
//===---------------------------------------------------------------------===//

Consider implementing a select with two conditional moves:

cmp x, y
moveq dst, a
movne dst, b

----------------------------------------------------------


%tmp1 = shl int %b, ubyte %c
%tmp4 = add int %a, %tmp1

compiles to

add r0, r0, r1, lsl r2

but

%tmp1 = shl int %b, ubyte %c
%tmp4 = add int %tmp1, %a

compiles to
mov r1, r1, lsl r2
add r0, r1, r0

----------------------------------------------------------

add an offset to FLDS/FLDD/FSTD/FSTS addressing mode

----------------------------------------------------------

the function

void %f() {
entry:
	call void %g( int 1, int 2, int 3, int 4, int 5 )
	ret void
}

declare void %g(int, int, int, int, int)

Only needs 8 bytes of stack space. We currently allocate 16.

----------------------------------------------------------

32 x 32 -> 64 multiplications currently uses two instructions. We
should try to declare smull and umull as returning two values.

----------------------------------------------------------

Implement addressing modes 2 (ldrb) and 3 (ldrsb)

----------------------------------------------------------