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4bfea803ed
After D98856 these tests will by default break (fatal_error) if any of the wrong interfaces are used, so there's no longer a need to have a RUN line that checks for a warning message emitted by the compiler.
68 lines
3.1 KiB
LLVM
68 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; Check that DAGCombiner is not asserting with mis-matched vector element count, "Vector element counts must match in SIGN_EXTEND_INREG".
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; Also no warning message of "warning: Possible incorrect use of EVT::getVectorNumElements() for scalable vector.".
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define <vscale x 4 x i32> @sext_inreg(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: sext_inreg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: sxth z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%in = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
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%splat = shufflevector <vscale x 4 x i32> %in, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%sext = shl <vscale x 4 x i32> %a, %splat
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%conv = ashr <vscale x 4 x i32> %sext, %splat
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ret <vscale x 4 x i32> %conv
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}
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define <vscale x 4 x i32> @ashr_shl(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: ashr_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl z0.s, z0.s, #8
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; CHECK-NEXT: asr z0.s, z0.s, #16
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; CHECK-NEXT: ret
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%in1 = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
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%splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%in2 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
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%splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%shl = shl <vscale x 4 x i32> %a, %splat1
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%r = ashr <vscale x 4 x i32> %shl, %splat2
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ret <vscale x 4 x i32> %r
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}
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define <vscale x 4 x i32> @ashr_shl_illegal_trunc_vec_ty(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: ashr_shl_illegal_trunc_vec_ty:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl z0.s, z0.s, #8
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; CHECK-NEXT: asr z0.s, z0.s, #11
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; CHECK-NEXT: ret
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%in1 = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
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%splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%in2 = insertelement <vscale x 4 x i32> undef, i32 11, i32 0
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%splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%shl = shl <vscale x 4 x i32> %a, %splat1
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%r = ashr <vscale x 4 x i32> %shl, %splat2
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ret <vscale x 4 x i32> %r
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}
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define <vscale x 4 x i32> @ashr_add_shl_nxv4i8(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: ashr_add_shl_nxv4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #16777216
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; CHECK-NEXT: mov z1.s, w8
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; CHECK-NEXT: lsl z0.s, z0.s, #24
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; CHECK-NEXT: add z0.s, z0.s, z1.s
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; CHECK-NEXT: asr z0.s, z0.s, #24
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; CHECK-NEXT: ret
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%in1 = insertelement <vscale x 4 x i32> undef, i32 24, i32 0
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%splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%in2 = insertelement <vscale x 4 x i32> undef, i32 16777216, i32 0
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%splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%conv = shl <vscale x 4 x i32> %a, %splat1
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%sext = add <vscale x 4 x i32> %conv, %splat2
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%conv1 = ashr <vscale x 4 x i32> %sext, %splat1
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ret <vscale x 4 x i32> %conv1
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}
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