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llvm-mirror/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll
Evandro Menezes fdd7b1d490 [AArch64] Split zero cycle feature more granularly
Split the `zcz` feature into specific ones got GP and FP registers, `zcz-gp`
and `zcz-fp`, respectively, while retaining the original feature option to
mean both.

Differential revision: https://reviews.llvm.org/D52621

llvm-svn: 343354
2018-09-28 19:05:09 +00:00

24 lines
777 B
LLVM

; RUN: llc < %s -mtriple=arm64-apple-ios -mattr=-zcm | FileCheck %s -check-prefixes=CHECK,NOT
; RUN: llc < %s -mtriple=arm64-apple-ios -mattr=+zcm | FileCheck %s -check-prefixes=CHECK,YES
; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=CHECK,YES
; rdar://12254953
define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind ssp {
entry:
; CHECK-LABEL: t:
; NOT: mov [[REG2:w[0-9]+]], w3
; NOT: mov [[REG1:w[0-9]+]], w2
; YES: mov [[REG2:x[0-9]+]], x3
; YES: mov [[REG1:x[0-9]+]], x2
; CHECK: bl _foo
; NOT: mov w0, [[REG1]]
; NOT: mov w1, [[REG2]]
; YES: mov x0, [[REG1]]
; YES: mov x1, [[REG2]]
%call = call i32 @foo(i32 %c, i32 %d) nounwind
%call1 = call i32 @foo(i32 %c, i32 %d) nounwind
unreachable
}
declare i32 @foo(i32, i32)