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af0734bc33
Before this instruction supported output values, it fit fairly naturally as a terminator. However, being a terminator while also supporting outputs causes some trouble, as the physreg->vreg COPY operations cannot be in the same block. Modeling it as a non-terminator allows it to be handled the same way as invoke is handled already. Most of the changes here were created by auditing all the existing users of MachineBasicBlock::isEHPad() and MachineBasicBlock::hasEHPadSuccessor(), and adding calls to isInlineAsmBrIndirectTarget or mayHaveInlineAsmBr, as appropriate. Reviewed By: nickdesaulniers, void Differential Revision: https://reviews.llvm.org/D79794
101 lines
3.2 KiB
LLVM
101 lines
3.2 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -filetype=obj -o - \
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; RUN: | llvm-objdump --triple=aarch64-unknown-linux-gnu -d - \
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; RUN: | FileCheck %s
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%struct.c = type { i1 (...)* }
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@l = common hidden local_unnamed_addr global i32 0, align 4
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; CHECK-LABEL: <test1>:
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; CHECK-LABEL: <$d.1>:
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; CHECK-LABEL: <$x.2>:
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; CHECK-NEXT: b 0x2c <$x.4>
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; CHECK-LABEL: <$x.4>:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ldr x30, [sp], #16
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; CHECK-NEXT: ret
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define hidden i32 @test1() {
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%1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %3, label %5
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3: ; preds = %0
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callbr void asm sideeffect "1: nop\0A\09.quad a\0A\09b ${1:l}\0A\09.quad ${0:c}", "i,X"(i32* null, i8* blockaddress(@test1, %7))
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to label %4 [label %7]
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4: ; preds = %3
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br label %7
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5: ; preds = %0
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%6 = tail call i32 bitcast (i32 (...)* @i to i32 ()*)()
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br label %7
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7: ; preds = %3, %4, %5
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%8 = phi i32 [ %6, %5 ], [ 0, %4 ], [ 0, %3 ]
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ret i32 %8
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}
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declare dso_local i32 @g(...) local_unnamed_addr
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declare dso_local i32 @i(...) local_unnamed_addr
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; CHECK-LABEL: <test2>:
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; CHECK: bl {{.*}} <test2+0x18>
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; CHECK-LABEL: <$d.5>:
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; CHECK-LABEL: <$x.6>:
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; CHECK-NEXT: b {{.*}} <test2+0x18>
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define hidden i32 @test2() local_unnamed_addr {
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%1 = load i32, i32* @l, align 4
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %10, label %3
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3: ; preds = %0
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%4 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
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%5 = icmp eq i32 %4, 0
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br i1 %5, label %6, label %7
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6: ; preds = %3
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callbr void asm sideeffect "1: nop\0A\09.quad b\0A\09b ${1:l}\0A\09.quad ${0:c}", "i,X"(i32* null, i8* blockaddress(@test2, %7))
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to label %10 [label %7]
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7: ; preds = %3
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%8 = tail call i32 bitcast (i32 (...)* @i to i32 ()*)()
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br label %10
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9: ; preds = %6
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br label %10
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10: ; preds = %7, %0, %6, %9
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ret i32 undef
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}
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; CHECK-LABEL: <test3>:
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; CHECK-LABEL: <$d.9>:
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; CHECK-LABEL: <$x.10>:
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; CHECK-NEXT: b {{.*}} <test3+0x18>
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; CHECK-LABEL: <$x.12>:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ldr x30, [sp], #16
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; CHECK-NEXT: ret
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define internal i1 @test3() {
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%1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %3, label %5
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3: ; preds = %0
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callbr void asm sideeffect "1: nop\0A\09.quad c\0A\09b ${1:l}\0A\09.quad ${0:c}", "i,X"(i32* null, i8* blockaddress(@test3, %8))
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to label %4 [label %8]
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4: ; preds = %3
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br label %8
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5: ; preds = %0
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%6 = tail call i32 bitcast (i32 (...)* @i to i32 ()*)()
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%7 = icmp ne i32 %6, 0
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br label %8
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8: ; preds = %3, %4, %5
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%9 = phi i1 [ %7, %5 ], [ false, %4 ], [ false, %3 ]
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ret i1 %9
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}
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