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093c73b470
This adds some conversion match patterns for which we want to keep the int values in FP registers using the corresponding NEON instructions (not the FP instructions) to avoid more costly int <-> fp register transfers. Differential Revision: https://reviews.llvm.org/D98956
75 lines
1.7 KiB
LLVM
75 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -o - %s -mattr=+neon,+fullfp16 | FileCheck %s
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define double @t1(double %x) {
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; CHECK-LABEL: t1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs d0, d0
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; CHECK-NEXT: scvtf d0, d0
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; CHECK-NEXT: ret
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entry:
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%conv = fptosi double %x to i64
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%conv1 = sitofp i64 %conv to double
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ret double %conv1
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}
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define float @t2(float %x) {
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; CHECK-LABEL: t2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs s0, s0
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; CHECK-NEXT: scvtf s0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = fptosi float %x to i32
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%conv1 = sitofp i32 %conv to float
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ret float %conv1
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}
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define half @t3(half %x) {
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; CHECK-LABEL: t3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs h0, h0
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; CHECK-NEXT: scvtf h0, h0
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; CHECK-NEXT: ret
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entry:
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%conv = fptosi half %x to i32
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%conv1 = sitofp i32 %conv to half
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ret half %conv1
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}
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define double @t4(double %x) {
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; CHECK-LABEL: t4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzu d0, d0
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; CHECK-NEXT: ucvtf d0, d0
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; CHECK-NEXT: ret
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entry:
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%conv = fptoui double %x to i64
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%conv1 = uitofp i64 %conv to double
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ret double %conv1
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}
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define float @t5(float %x) {
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; CHECK-LABEL: t5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzu s0, s0
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; CHECK-NEXT: ucvtf s0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = fptoui float %x to i32
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%conv1 = uitofp i32 %conv to float
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ret float %conv1
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}
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define half @t6(half %x) {
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; CHECK-LABEL: t6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzu h0, h0
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; CHECK-NEXT: ucvtf h0, h0
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; CHECK-NEXT: ret
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entry:
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%conv = fptoui half %x to i32
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%conv1 = uitofp i32 %conv to half
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ret half %conv1
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}
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