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025fa2bbb5
Summary: The Pointer Authentication Extension (PAC) was added in Armv8.3-A. Some instructions are implemented in the HINT space to allow compiling code common to CPUs regardless of whether they feature PAC or not, and still benefit from PAC protection in the PAC-enabled CPUs. The 8.3-specific mnemonics were currently enabled in any architecture, and LLVM was emitting them in assembly files when PAC code generation was enabled. This was ok for compilations where both LLVM codegen and the integrated assembler were used. However, the LLVM codegen was not compatible with other assemblers (e.g. GAS). Given the fact that the approach from these assemblers (i.e. to disallow Armv8.3-A mnemonics if compiling for Armv8.2-A or lower) is entirely reasonable, this patch makes LLVM to emit HINT when building for Armv8.2-A and below, instead of PACIASP, AUTIASP and friends. Then, LLVM assembly should be compatible with other assemblers. Reviewers: samparker, chill, LukeCheeseman Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71658
80 lines
2.8 KiB
LLVM
80 lines
2.8 KiB
LLVM
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
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; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
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; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
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; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
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; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
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define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
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; CHECK-LABEL: a: // @a
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; CHECK: .cfi_b_key_frame
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; V8A-NEXT: hint #27
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; V83A-NEXT: pacibsp
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; CHECK-NEXT: .cfi_negate_ra_state
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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store i32 1, i32* %1, align 4
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store i32 2, i32* %2, align 4
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store i32 3, i32* %3, align 4
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store i32 4, i32* %4, align 4
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store i32 5, i32* %5, align 4
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store i32 6, i32* %6, align 4
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call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
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ret i64 %x
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}
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define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
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; CHECK-LABEL: b: // @b
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; CHECK: .cfi_b_key_frame
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; V8A-NEXT: hint #27
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; V83A-NEXT: pacibsp
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; CHECK-NEXT: .cfi_negate_ra_state
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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store i32 1, i32* %1, align 4
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store i32 2, i32* %2, align 4
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store i32 3, i32* %3, align 4
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store i32 4, i32* %4, align 4
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store i32 5, i32* %5, align 4
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store i32 6, i32* %6, align 4
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call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
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ret i64 %x
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}
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define i64 @c(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
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; CHECK-LABEL: c: // @c
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; CHECK: .cfi_b_key_frame
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; V8A-NEXT: hint #27
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; V83A-NEXT: pacibsp
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; CHECK-NEXT: .cfi_negate_ra_state
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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store i32 1, i32* %1, align 4
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store i32 2, i32* %2, align 4
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store i32 3, i32* %3, align 4
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store i32 4, i32* %4, align 4
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store i32 5, i32* %5, align 4
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store i32 6, i32* %6, align 4
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call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
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ret i64 %x
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}
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; Outlined function is leaf-function => don't sign it
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; CHECK-LABEL: OUTLINED_FUNCTION_0:
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; CHECK-NOT: .cfi_b_key_frame
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; CHECK-NOT: paci{{[a,b]}}sp
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; CHECK-NOT: hint #2{{[5,7]}}
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; CHECK-NOT: .cfi_negate_ra_state
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; CHECK-NOT: auti{{[a,b]}}sp
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