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100 lines
3.0 KiB
LLVM
100 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-eabi -mattr=+fullfp16 %s -o - | FileCheck %s
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; The llvm.aarch64_neon_rbit intrinsic should be auto-upgraded to the
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; target-independent bitreverse intrinsic.
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declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) nounwind readnone
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define <8 x i8> @rbit_8x8(<8 x i8> %A) nounwind {
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; CHECK-LABEL: rbit_8x8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rbit v0.8b, v0.8b
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; CHECK-NEXT: ret
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %A)
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ret <8 x i8> %tmp3
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}
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declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) nounwind readnone
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define <16 x i8> @rbit_16x8(<16 x i8> %A) nounwind {
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; CHECK-LABEL: rbit_16x8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rbit v0.16b, v0.16b
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; CHECK-NEXT: ret
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%tmp3 = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %A)
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ret <16 x i8> %tmp3
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}
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declare <4 x i16> @llvm.aarch64.neon.rbit.v4i16(<4 x i16>) nounwind readnone
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define <4 x i16> @rbit_4x16(<4 x i16> %A) nounwind {
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; CHECK-LABEL: rbit_4x16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev16 v0.8b, v0.8b
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; CHECK-NEXT: rbit v0.8b, v0.8b
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; CHECK-NEXT: ret
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.rbit.v4i16(<4 x i16> %A)
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ret <4 x i16> %tmp3
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}
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declare <8 x i16> @llvm.aarch64.neon.rbit.v8i16(<8 x i16>) nounwind readnone
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define <8 x i16> @rbit_8x16(<8 x i16> %A) {
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; CHECK-LABEL: rbit_8x16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev16 v0.16b, v0.16b
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; CHECK-NEXT: rbit v0.16b, v0.16b
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; CHECK-NEXT: ret
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.rbit.v8i16(<8 x i16> %A)
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ret <8 x i16> %tmp3
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}
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declare <2 x i32> @llvm.aarch64.neon.rbit.v2i32(<2 x i32>) nounwind readnone
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define <2 x i32> @rbit_2x32(<2 x i32> %A) {
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; CHECK-LABEL: rbit_2x32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev32 v0.8b, v0.8b
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; CHECK-NEXT: rbit v0.8b, v0.8b
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; CHECK-NEXT: ret
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.rbit.v2i32(<2 x i32> %A)
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ret <2 x i32> %tmp3
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}
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declare <4 x i32> @llvm.aarch64.neon.rbit.v4i32(<4 x i32>) nounwind readnone
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define <4 x i32> @rbit_4x32(<4 x i32> %A) {
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; CHECK-LABEL: rbit_4x32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev32 v0.16b, v0.16b
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; CHECK-NEXT: rbit v0.16b, v0.16b
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; CHECK-NEXT: ret
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.rbit.v4i32(<4 x i32> %A)
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ret <4 x i32> %tmp3
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}
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declare <1 x i64> @llvm.aarch64.neon.rbit.v1i64(<1 x i64>) readnone
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define <1 x i64> @rbit_1x64(<1 x i64> %A) {
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; CHECK-LABEL: rbit_1x64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev64 v0.8b, v0.8b
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; CHECK-NEXT: rbit v0.8b, v0.8b
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; CHECK-NEXT: ret
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%tmp3 = call <1 x i64> @llvm.aarch64.neon.rbit.v1i64(<1 x i64> %A)
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ret <1 x i64> %tmp3
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}
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declare <2 x i64> @llvm.aarch64.neon.rbit.v2i64(<2 x i64>) readnone
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define <2 x i64> @rbit_2x64(<2 x i64> %A) {
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; CHECK-LABEL: rbit_2x64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev64 v0.16b, v0.16b
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; CHECK-NEXT: rbit v0.16b, v0.16b
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; CHECK-NEXT: ret
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.rbit.v2i64(<2 x i64> %A)
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ret <2 x i64> %tmp3
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}
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