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5ca2e09258
This patch implements the __rndr and __rndrrs intrinsics to provide access to the random number instructions introduced in Armv8.5-A. They are only defined for the AArch64 execution state and are available when __ARM_FEATURE_RNG is defined. These intrinsics store the random number in their pointer argument and return a status code if the generation succeeded. The difference between __rndr __rndrrs, is that the latter intrinsic reseeds the random number generator. The instructions write the NZCV flags indicating the success of the operation that we can then read with a CSET. [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics [2] https://bugs.llvm.org/show_bug.cgi?id=47838 Differential Revision: https://reviews.llvm.org/D98264 Change-Id: I8f92e7bf5b450e5da3e59943b53482edf0df6efc
41 lines
1.1 KiB
LLVM
41 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand %s -o - | FileCheck %s
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define i32 @rndr(i64* %__addr) {
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; CHECK-LABEL: rndr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mrs x9, RNDR
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: and w8, w8, #0x1
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; CHECK-NEXT: str x9, [x0]
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: ret
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%1 = tail call { i64, i1 } @llvm.aarch64.rndr()
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%2 = extractvalue { i64, i1 } %1, 0
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%3 = extractvalue { i64, i1 } %1, 1
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store i64 %2, i64* %__addr, align 8
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%4 = zext i1 %3 to i32
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ret i32 %4
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}
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define i32 @rndrrs(i64* %__addr) {
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; CHECK-LABEL: rndrrs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mrs x9, RNDRRS
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: and w8, w8, #0x1
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; CHECK-NEXT: str x9, [x0]
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: ret
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%1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
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%2 = extractvalue { i64, i1 } %1, 0
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%3 = extractvalue { i64, i1 } %1, 1
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store i64 %2, i64* %__addr, align 8
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%4 = zext i1 %3 to i32
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ret i32 %4
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}
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declare { i64, i1 } @llvm.aarch64.rndr()
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declare { i64, i1 } @llvm.aarch64.rndrrs()
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