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https://github.com/RPCS3/llvm-mirror.git
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4bfea803ed
After D98856 these tests will by default break (fatal_error) if any of the wrong interfaces are used, so there's no longer a need to have a RUN line that checks for a warning message emitted by the compiler.
737 lines
22 KiB
LLVM
737 lines
22 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; FP_EXTEND
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;
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define <vscale x 2 x float> @fcvts_nxv2f16(<vscale x 2 x half> %a) {
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; CHECK-LABEL: fcvts_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvt z0.s, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fpext <vscale x 2 x half> %a to <vscale x 2 x float>
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ret <vscale x 2 x float> %res
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}
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define <vscale x 4 x float> @fcvts_nxv4f16(<vscale x 4 x half> %a) {
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; CHECK-LABEL: fcvts_nxv4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvt z0.s, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fpext <vscale x 4 x half> %a to <vscale x 4 x float>
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ret <vscale x 4 x float> %res
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}
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define <vscale x 2 x double> @fcvtd_nxv2f16(<vscale x 2 x half> %a) {
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; CHECK-LABEL: fcvtd_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvt z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fpext <vscale x 2 x half> %a to <vscale x 2 x double>
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ret <vscale x 2 x double> %res
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}
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define <vscale x 2 x double> @fcvtd_nxv2f32(<vscale x 2 x float> %a) {
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; CHECK-LABEL: fcvtd_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvt z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fpext <vscale x 2 x float> %a to <vscale x 2 x double>
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ret <vscale x 2 x double> %res
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}
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;
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; FP_ROUND
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;
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define <vscale x 2 x half> @fcvth_nxv2f32(<vscale x 2 x float> %a) {
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; CHECK-LABEL: fcvth_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvt z0.h, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptrunc <vscale x 2 x float> %a to <vscale x 2 x half>
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ret <vscale x 2 x half> %res
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}
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define <vscale x 4 x half> @fcvth_nxv4f32(<vscale x 4 x float> %a) {
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; CHECK-LABEL: fcvth_nxv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvt z0.h, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptrunc <vscale x 4 x float> %a to <vscale x 4 x half>
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ret <vscale x 4 x half> %res
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}
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define <vscale x 2 x half> @fcvth_nxv2f64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: fcvth_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvt z0.h, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = fptrunc <vscale x 2 x double> %a to <vscale x 2 x half>
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ret <vscale x 2 x half> %res
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}
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define <vscale x 2 x float> @fcvts_nxv2f64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: fcvts_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvt z0.s, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = fptrunc <vscale x 2 x double> %a to <vscale x 2 x float>
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ret <vscale x 2 x float> %res
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}
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;
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; FP_TO_SINT
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;
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define <vscale x 2 x i16> @fcvtzs_h_nxv2f16(<vscale x 2 x half> %a) {
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; CHECK-LABEL: fcvtzs_h_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i16>
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ret <vscale x 2 x i16> %res
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}
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define <vscale x 2 x i16> @fcvtzs_h_nxv2f32(<vscale x 2 x float> %a) {
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; CHECK-LABEL: fcvtzs_h_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i16>
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ret <vscale x 2 x i16> %res
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}
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define <vscale x 2 x i16> @fcvtzs_h_nxv2f64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: fcvtzs_h_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i16>
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ret <vscale x 2 x i16> %res
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}
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define <vscale x 4 x i16> @fcvtzs_h_nxv4f16(<vscale x 4 x half> %a) {
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; CHECK-LABEL: fcvtzs_h_nxv4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>
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ret <vscale x 4 x i16> %res
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}
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define <vscale x 4 x i16> @fcvtzs_h_nxv4f32(<vscale x 4 x float> %a) {
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; CHECK-LABEL: fcvtzs_h_nxv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>
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ret <vscale x 4 x i16> %res
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}
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define <vscale x 8 x i16> @fcvtzs_h_nxv8f16(<vscale x 8 x half> %a) {
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; CHECK-LABEL: fcvtzs_h_nxv8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 8 x half> %a to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 2 x i32> @fcvtzs_s_nxv2f16(<vscale x 2 x half> %a) {
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; CHECK-LABEL: fcvtzs_s_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i32>
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 2 x i32> @fcvtzs_s_nxv2f32(<vscale x 2 x float> %a) {
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; CHECK-LABEL: fcvtzs_s_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i32>
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 2 x i32> @fcvtzs_s_nxv2f64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: fcvtzs_s_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i32>
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 4 x i32> @fcvtzs_s_nxv4f16(<vscale x 4 x half> %a) {
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; CHECK-LABEL: fcvtzs_s_nxv4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @fcvtzs_s_nxv4f32(<vscale x 4 x float> %a) {
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; CHECK-LABEL: fcvtzs_s_nxv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @fcvtzs_d_nxv2f16(<vscale x 2 x half> %a) {
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; CHECK-LABEL: fcvtzs_d_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @fcvtzs_d_nxv2f32(<vscale x 2 x float> %a) {
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; CHECK-LABEL: fcvtzs_d_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @fcvtzs_d_nxv2f64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: fcvtzs_d_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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;
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; FP_TO_UINT
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;
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; NOTE: Using fcvtzs is safe as fptoui overflow is considered poison and a
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; 64bit signed value encompasses the entire range of a 16bit unsigned value
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define <vscale x 2 x i16> @fcvtzu_h_nxv2f16(<vscale x 2 x half> %a) {
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; CHECK-LABEL: fcvtzu_h_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i16>
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ret <vscale x 2 x i16> %res
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}
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define <vscale x 2 x i16> @fcvtzu_h_nxv2f32(<vscale x 2 x float> %a) {
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; CHECK-LABEL: fcvtzu_h_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i16>
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ret <vscale x 2 x i16> %res
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}
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define <vscale x 2 x i16> @fcvtzu_h_nxv2f64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: fcvtzu_h_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i16>
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ret <vscale x 2 x i16> %res
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}
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define <vscale x 4 x i16> @fcvtzu_h_nxv4f16(<vscale x 4 x half> %a) {
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; CHECK-LABEL: fcvtzu_h_nxv4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>
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ret <vscale x 4 x i16> %res
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}
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define <vscale x 4 x i16> @fcvtzu_h_nxv4f32(<vscale x 4 x float> %a) {
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; CHECK-LABEL: fcvtzu_h_nxv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>
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ret <vscale x 4 x i16> %res
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}
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define <vscale x 8 x i16> @fcvtzu_h_nxv8f16(<vscale x 8 x half> %a) {
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; CHECK-LABEL: fcvtzu_h_nxv8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 8 x half> %a to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 2 x i32> @fcvtzu_s_nxv2f16(<vscale x 2 x half> %a) {
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; CHECK-LABEL: fcvtzu_s_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i32>
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 2 x i32> @fcvtzu_s_nxv2f32(<vscale x 2 x float> %a) {
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; CHECK-LABEL: fcvtzu_s_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i32>
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 2 x i32> @fcvtzu_s_nxv2f64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: fcvtzu_s_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i32>
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 4 x i32> @fcvtzu_s_nxv4f16(<vscale x 4 x half> %a) {
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; CHECK-LABEL: fcvtzu_s_nxv4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @fcvtzu_s_nxv4f32(<vscale x 4 x float> %a) {
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; CHECK-LABEL: fcvtzu_s_nxv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 4 x float> %a to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @fcvtzu_d_nxv2f16(<vscale x 2 x half> %a) {
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; CHECK-LABEL: fcvtzu_d_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @fcvtzu_d_nxv2f32(<vscale x 2 x float> %a) {
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; CHECK-LABEL: fcvtzu_d_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @fcvtzu_d_nxv2f64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: fcvtzu_d_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i64>
|
|
ret <vscale x 2 x i64> %res
|
|
}
|
|
|
|
; SINT_TO_FP
|
|
|
|
define <vscale x 2 x half> @scvtf_h_nxv2i1(<vscale x 2 x i1> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv2i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x half>
|
|
ret <vscale x 2 x half> %res
|
|
}
|
|
|
|
define <vscale x 2 x half> @scvtf_h_nxv2i16(<vscale x 2 x i16> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i16> %a to <vscale x 2 x half>
|
|
ret <vscale x 2 x half> %res
|
|
}
|
|
|
|
define <vscale x 2 x half> @scvtf_h_nxv2i32(<vscale x 2 x i32> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x half>
|
|
ret <vscale x 2 x half> %res
|
|
}
|
|
|
|
define <vscale x 2 x half> @scvtf_h_nxv2i64(<vscale x 2 x i64> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x half>
|
|
ret <vscale x 2 x half> %res
|
|
}
|
|
|
|
define <vscale x 4 x half> @scvtf_h_nxv4i1(<vscale x 4 x i1> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv4i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 4 x i1> %a to <vscale x 4 x half>
|
|
ret <vscale x 4 x half> %res
|
|
}
|
|
|
|
define <vscale x 4 x half> @scvtf_h_nxv4i16(<vscale x 4 x i16> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 4 x i16> %a to <vscale x 4 x half>
|
|
ret <vscale x 4 x half> %res
|
|
}
|
|
|
|
define <vscale x 4 x half> @scvtf_h_nxv4i32(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 4 x i32> %a to <vscale x 4 x half>
|
|
ret <vscale x 4 x half> %res
|
|
}
|
|
|
|
define <vscale x 8 x half> @scvtf_h_nxv8i1(<vscale x 8 x i1> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv8i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: ptrue p0.h
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 8 x i1> %a to <vscale x 8 x half>
|
|
ret <vscale x 8 x half> %res
|
|
}
|
|
|
|
define <vscale x 8 x half> @scvtf_h_nxv8i16(<vscale x 8 x i16> %a) {
|
|
; CHECK-LABEL: scvtf_h_nxv8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h
|
|
; CHECK-NEXT: scvtf z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 8 x i16> %a to <vscale x 8 x half>
|
|
ret <vscale x 8 x half> %res
|
|
}
|
|
|
|
define <vscale x 2 x float> @scvtf_s_nxv2i1(<vscale x 2 x i1> %a) {
|
|
; CHECK-LABEL: scvtf_s_nxv2i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.s, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x float>
|
|
ret <vscale x 2 x float> %res
|
|
}
|
|
|
|
define <vscale x 2 x float> @scvtf_s_nxv2i32(<vscale x 2 x i32> %a) {
|
|
; CHECK-LABEL: scvtf_s_nxv2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x float>
|
|
ret <vscale x 2 x float> %res
|
|
}
|
|
|
|
define <vscale x 2 x float> @scvtf_s_nxv2i64(<vscale x 2 x i64> %a) {
|
|
; CHECK-LABEL: scvtf_s_nxv2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.s, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x float>
|
|
ret <vscale x 2 x float> %res
|
|
}
|
|
|
|
define <vscale x 4 x float> @scvtf_s_nxv4i1(<vscale x 4 x i1> %a) {
|
|
; CHECK-LABEL: scvtf_s_nxv4i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: scvtf z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 4 x i1> %a to <vscale x 4 x float>
|
|
ret <vscale x 4 x float> %res
|
|
}
|
|
|
|
define <vscale x 4 x float> @scvtf_s_nxv4i32(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: scvtf_s_nxv4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: scvtf z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 4 x i32> %a to <vscale x 4 x float>
|
|
ret <vscale x 4 x float> %res
|
|
}
|
|
|
|
define <vscale x 2 x double> @scvtf_d_nxv2i1(<vscale x 2 x i1> %a) {
|
|
; CHECK-LABEL: scvtf_d_nxv2i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x double>
|
|
ret <vscale x 2 x double> %res
|
|
}
|
|
|
|
define <vscale x 2 x double> @scvtf_d_nxv2i32(<vscale x 2 x i32> %a) {
|
|
; CHECK-LABEL: scvtf_d_nxv2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x double>
|
|
ret <vscale x 2 x double> %res
|
|
}
|
|
|
|
define <vscale x 2 x double> @scvtf_d_nxv2i64(<vscale x 2 x i64> %a) {
|
|
; CHECK-LABEL: scvtf_d_nxv2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x double>
|
|
ret <vscale x 2 x double> %res
|
|
}
|
|
|
|
; UINT_TO_FP
|
|
|
|
define <vscale x 2 x half> @ucvtf_h_nxv2i1(<vscale x 2 x i1> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv2i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x half>
|
|
ret <vscale x 2 x half> %res
|
|
}
|
|
|
|
define <vscale x 2 x half> @ucvtf_h_nxv2i16(<vscale x 2 x i16> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i16> %a to <vscale x 2 x half>
|
|
ret <vscale x 2 x half> %res
|
|
}
|
|
|
|
define <vscale x 2 x half> @ucvtf_h_nxv2i32(<vscale x 2 x i32> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x half>
|
|
ret <vscale x 2 x half> %res
|
|
}
|
|
|
|
define <vscale x 2 x half> @ucvtf_h_nxv2i64(<vscale x 2 x i64> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x half>
|
|
ret <vscale x 2 x half> %res
|
|
}
|
|
|
|
define <vscale x 4 x half> @ucvtf_h_nxv4i1(<vscale x 4 x i1> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv4i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x1
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 4 x i1> %a to <vscale x 4 x half>
|
|
ret <vscale x 4 x half> %res
|
|
}
|
|
|
|
define <vscale x 4 x half> @ucvtf_h_nxv4i16(<vscale x 4 x i16> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 4 x i16> %a to <vscale x 4 x half>
|
|
ret <vscale x 4 x half> %res
|
|
}
|
|
|
|
define <vscale x 4 x half> @ucvtf_h_nxv4i32(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 4 x i32> %a to <vscale x 4 x half>
|
|
ret <vscale x 4 x half> %res
|
|
}
|
|
|
|
define <vscale x 8 x half> @ucvtf_h_nxv8i1(<vscale x 8 x i1> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv8i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.h, p0/z, #1 // =0x1
|
|
; CHECK-NEXT: ptrue p0.h
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 8 x i1> %a to <vscale x 8 x half>
|
|
ret <vscale x 8 x half> %res
|
|
}
|
|
|
|
define <vscale x 8 x half> @ucvtf_h_nxv8i16(<vscale x 8 x i16> %a) {
|
|
; CHECK-LABEL: ucvtf_h_nxv8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h
|
|
; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 8 x i16> %a to <vscale x 8 x half>
|
|
ret <vscale x 8 x half> %res
|
|
}
|
|
|
|
define <vscale x 2 x float> @ucvtf_s_nxv2i1(<vscale x 2 x i1> %a) {
|
|
; CHECK-LABEL: ucvtf_s_nxv2i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x float>
|
|
ret <vscale x 2 x float> %res
|
|
}
|
|
|
|
define <vscale x 2 x float> @ucvtf_s_nxv2i32(<vscale x 2 x i32> %a) {
|
|
; CHECK-LABEL: ucvtf_s_nxv2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x float>
|
|
ret <vscale x 2 x float> %res
|
|
}
|
|
|
|
define <vscale x 2 x float> @ucvtf_s_nxv2i64(<vscale x 2 x i64> %a) {
|
|
; CHECK-LABEL: ucvtf_s_nxv2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x float>
|
|
ret <vscale x 2 x float> %res
|
|
}
|
|
|
|
define <vscale x 4 x float> @ucvtf_s_nxv4i1(<vscale x 4 x i1> %a) {
|
|
; CHECK-LABEL: ucvtf_s_nxv4i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x1
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 4 x i1> %a to <vscale x 4 x float>
|
|
ret <vscale x 4 x float> %res
|
|
}
|
|
|
|
define <vscale x 4 x float> @ucvtf_s_nxv4i32(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: ucvtf_s_nxv4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 4 x i32> %a to <vscale x 4 x float>
|
|
ret <vscale x 4 x float> %res
|
|
}
|
|
|
|
define <vscale x 2 x double> @ucvtf_d_nxv2i1(<vscale x 2 x i1> %a) {
|
|
; CHECK-LABEL: ucvtf_d_nxv2i1:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x double>
|
|
ret <vscale x 2 x double> %res
|
|
}
|
|
|
|
define <vscale x 2 x double> @ucvtf_d_nxv2i32(<vscale x 2 x i32> %a) {
|
|
; CHECK-LABEL: ucvtf_d_nxv2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x double>
|
|
ret <vscale x 2 x double> %res
|
|
}
|
|
|
|
define <vscale x 2 x double> @ucvtf_d_nxv2i64(<vscale x 2 x i64> %a) {
|
|
; CHECK-LABEL: ucvtf_d_nxv2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
%res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x double>
|
|
ret <vscale x 2 x double> %res
|
|
}
|