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be488ff93c
Follow up to D101357 / 3fa6510f6.
Supersedes D102330.
Goal: Use flags setting rdffrs instead of rdffr + ptest.
Problem: RDFFR_P doesn't have have a flags setting equivalent.
Solution: in instcombine, canonicalize to RDFFR_PP at the IR level, and
rely on RDFFR_PP+PTEST => RDFFRS_PP optimization in
AArch64InstrInfo::optimizePTestInstr.
While here:
* Test that rdffr.z+ptest generates a rdffrs.
* Use update_{test,llc}_checks.py on the tests.
* Use sve attribute on functions.
Differential Revision: https://reviews.llvm.org/D102623
74 lines
1.9 KiB
LLVM
74 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; RDFFR
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;
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define <vscale x 16 x i1> @rdffr() #0 {
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; CHECK-LABEL: rdffr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdffr p0.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr()
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 16 x i1> @rdffr_z(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: rdffr_z:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdffr p0.b, p0/z
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg)
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ret <vscale x 16 x i1> %out
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}
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; Test that rdffr.z followed by ptest optimizes to flags-setting rdffrs.
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define i1 @rdffr_z_ptest(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: rdffr_z_ptest:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdffrs p0.b, p0/z
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%rdffr = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg)
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%out = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %rdffr)
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ret i1 %out
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}
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;
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; SETFFR
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;
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define void @set_ffr() #0 {
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; CHECK-LABEL: set_ffr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: setffr
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.setffr()
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ret void
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}
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;
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; WRFFR
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;
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define void @wrffr(<vscale x 16 x i1> %a) #0 {
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; CHECK-LABEL: wrffr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: wrffr p0.b
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1> %a)
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ret void
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr()
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declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>)
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declare void @llvm.aarch64.sve.setffr()
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declare void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1>)
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declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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attributes #0 = { "target-features"="+sve" }
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