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For reg+imm SVE addressing mode imm is implictly scaled by VL, making them impractical for truely immediate offsets. However, if the offset can be unscaled based on the storage element type we can use the reg+reg SVE addressing mode and thus either reduce the number of generate add instructions or replace them with a mov instruction that can be hoisted from the hot code path. Differential Revision: https://reviews.llvm.org/D106744
171 lines
6.4 KiB
LLVM
171 lines
6.4 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm -asm-verbose=0 < %s | FileCheck %s
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;
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; LD1ROB
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;
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define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pg, i8* %a) nounwind {
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; CHECK-LABEL: ld1rob_i8:
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; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, #32]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 32
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%load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
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ret <vscale x 16 x i8> %load
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}
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;
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; LD1ROH
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;
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define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pg, i16* %a) nounwind {
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; CHECK-LABEL: ld1roh_i16:
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; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 32
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%load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pg, i16* %base)
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ret <vscale x 8 x i16> %load
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}
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define <vscale x 8 x half> @ld1roh_f16(<vscale x 8 x i1> %pg, half* %a) nounwind {
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; CHECK-LABEL: ld1roh_f16:
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; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]
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; CHECK-NEXT: ret
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%base = getelementptr half, half* %a, i64 32
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%load = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pg, half* %base)
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ret <vscale x 8 x half> %load
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}
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define <vscale x 8 x bfloat> @ld1roh_bf16(<vscale x 8 x i1> %pg, bfloat* %a) nounwind #0 {
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; CHECK-LABEL: ld1roh_bf16:
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; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]
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; CHECK-NEXT: ret
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%base = getelementptr bfloat, bfloat* %a, i64 32
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%load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1> %pg, bfloat* %base)
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ret <vscale x 8 x bfloat> %load
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}
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;
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; LD1ROW
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;
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define<vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pg, i32* %a) nounwind {
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; CHECK-LABEL: ld1row_i32:
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; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, #128]
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; CHECK-NEXT: ret
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%base = getelementptr i32, i32* %a, i64 32
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%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pg, i32* %base)
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ret <vscale x 4 x i32> %load
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}
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define<vscale x 4 x float> @ld1row_f32(<vscale x 4 x i1> %pg, float* %a) nounwind {
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; CHECK-LABEL: ld1row_f32:
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; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, #128]
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; CHECK-NEXT: ret
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%base = getelementptr float, float* %a, i64 32
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%load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pg, float* %base)
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ret <vscale x 4 x float> %load
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}
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;
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; LD1ROD
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;
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define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pg, i64* %a) nounwind {
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; CHECK-LABEL: ld1rod_i64:
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; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #-64]
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; CHECK-NEXT: ret
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%base = getelementptr i64, i64* %a, i64 -8
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%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pg, i64* %base)
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ret <vscale x 2 x i64> %load
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}
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define <vscale x 2 x double> @ld1rod_f64(<vscale x 2 x i1> %pg, double* %a) nounwind {
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; CHECK-LABEL: ld1rod_f64:
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; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #-128]
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; CHECK-NEXT: ret
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%base = getelementptr double, double* %a, i64 -16
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%load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pg, double* %base)
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ret <vscale x 2 x double> %load
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}
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;;;;;;;;;;;;;;
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; range checks: immediate must be a multiple of 32 in the range -256, ..., 224
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; lower bound
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define <vscale x 16 x i8> @ld1rob_i8_lower_bound(<vscale x 16 x i1> %pg, i8* %a) nounwind {
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; CHECK-LABEL: ld1rob_i8_lower_bound:
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; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, #-256]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 -256
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%load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
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ret <vscale x 16 x i8> %load
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}
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; below lower bound
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define <vscale x 8 x i16> @ld1roh_i16_below_lower_bound(<vscale x 8 x i1> %pg, i16* %a) nounwind {
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; CHECK-LABEL: ld1roh_i16_below_lower_bound:
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; CHECK-NEXT: mov x[[IDX:[0-9]+]], #-129
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; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x[[IDX]], lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 -129
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%load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pg, i16* %base)
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ret <vscale x 8 x i16> %load
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}
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define <vscale x 16 x i8> @ld1rob_i8_below_lower_bound_01(<vscale x 16 x i1> %pg, i8* %a) nounwind {
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; CHECK-LABEL: ld1rob_i8_below_lower_bound_01:
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; CHECK-NEXT: mov x[[OFFSET:[0-9]+]], #-257
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; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, x[[OFFSET]]]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 -257
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%load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
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ret <vscale x 16 x i8> %load
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}
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; not a multiple of 32
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define<vscale x 4 x i32> @ld1row_i32_not_multiple(<vscale x 4 x i1> %pg, i32* %a) nounwind {
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; CHECK-LABEL: ld1row_i32_not_multiple:
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; CHECK-NEXT: mov x[[IDX:[0-9]+]], #3
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; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, x[[IDX]], lsl #2]
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; CHECK-NEXT: ret
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%base = getelementptr i32, i32* %a, i64 3
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%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pg, i32* %base)
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ret <vscale x 4 x i32> %load
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}
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; upper bound
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define <vscale x 2 x i64> @ld1rod_i64_upper_bound(<vscale x 2 x i1> %pg, i64* %a) nounwind {
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; CHECK-LABEL: ld1rod_i64_upper_bound:
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; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #224]
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; CHECK-NEXT: ret
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%base = getelementptr i64, i64* %a, i64 28
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%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pg, i64* %base)
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ret <vscale x 2 x i64> %load
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}
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define <vscale x 16 x i8> @ld1rob_i8_beyond_upper_bound(<vscale x 16 x i1> %pg, i8* %a) nounwind {
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; CHECK-LABEL: ld1rob_i8_beyond_upper_bound:
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; CHECK-NEXT: mov w[[OFFSET:[0-9]+]], #225
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; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, x[[OFFSET]]]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 225
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%load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
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ret <vscale x 16 x i8> %load
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, i8*)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, i16*)
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declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, half*)
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declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1>, bfloat*)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, i32*)
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declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, float*)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, i64*)
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declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, double*)
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+f64mm,+bf16" }
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