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f69dc8533f
This avoids the use of the vector unit for copying from scalar to vector. There is an extra ptrue instruction, but a predicate register with the ptrue pattern populated is likely to be free in the context of real code. Tests were generated from a template to cover the axes mentioned at the top of the test file. Co-authored-by: Francesco Petrogalli <francesco.petrogalli@arm.com> Differential Revision: https://reviews.llvm.org/D103170
39 lines
1.4 KiB
LLVM
39 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; These tests are here to ensure we don't get a selection error caused
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; by performPostLD1Combine, which should bail out if the return
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; type is a scalable vector
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define <vscale x 4 x i32> @test_post_ld1_insert(i32* %a, i32** %ptr, i64 %inc) {
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; CHECK-LABEL: test_post_ld1_insert:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: add x9, x0, x2, lsl #2
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; CHECK-NEXT: str x9, [x1]
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: ret
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%load = load i32, i32* %a
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%ins = insertelement <vscale x 4 x i32> undef, i32 %load, i32 0
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%gep = getelementptr i32, i32* %a, i64 %inc
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store i32* %gep, i32** %ptr
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ret <vscale x 4 x i32> %ins
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}
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define <vscale x 2 x double> @test_post_ld1_dup(double* %a, double** %ptr, i64 %inc) {
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; CHECK-LABEL: test_post_ld1_dup:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x0]
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; CHECK-NEXT: add x8, x0, x2, lsl #3
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; CHECK-NEXT: str x8, [x1]
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; CHECK-NEXT: ret
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%load = load double, double* %a
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%dup = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %load)
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%gep = getelementptr double, double* %a, i64 %inc
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store double* %gep, double** %ptr
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ret <vscale x 2 x double> %dup
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double)
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