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llvm-mirror/test/CodeGen/AArch64/swift-async-reg.ll
Tim Northover 5661b7eb80 IR+AArch64: add a "swiftasync" argument attribute.
This extends any frame record created in the function to include that
parameter, passed in X22.

The new record looks like [X22, FP, LR] in memory, and FP is stored with 0b0001
in bits 63:60 (CodeGen assumes they are 0b0000 in normal operation). The effect
of this is that tools walking the stack should expect to see one of three
values there:

  * 0b0000 => a normal, non-extended record with just [FP, LR]
  * 0b0001 => the extended record [X22, FP, LR]
  * 0b1111 => kernel space, and a non-extended record.

All other values are currently reserved.

If compiling for arm64e this context pointer is address-discriminated with the
discriminator 0xc31a and the DB (process-specific) key.

There is also an "i8** @llvm.swift.async.context.addr()" intrinsic providing
front-ends access to this slot (and forcing its creation initialized to nullptr
if necessary).
2021-05-14 11:43:58 +01:00

19 lines
435 B
LLVM

; RUN: llc -mtriple=arm64-apple-ios %s -o - | FileCheck %s
; RUN: llc -mtriple=arm64-apple-ios %s -o - -global-isel | FileCheck %s
; RUN: llc -mtriple=arm64-apple-ios %s -o - -fast-isel | FileCheck %s
define i8* @argument(i8* swiftasync %in) {
; CHECK-LABEL: argument:
; CHECK: mov x0, x22
ret i8* %in
}
define void @call(i8* %in) {
; CHECK-LABEL: call:
; CHECK: mov x22, x0
call i8* @argument(i8* swiftasync %in)
ret void
}