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llvm-mirror/test/CodeGen/AArch64/uaddo.ll
Sanjay Patel 15f35365a5 [CGP] add special-cases to form unsigned add with overflow (PR40486)
There's likely a missed IR canonicalization for at least 1 of these
patterns. Otherwise, we wouldn't have needed the pattern-matching
enhancement in D57516.

Note that -- unlike usubo added with D57789 -- the TLI hook for
this transform defaults to 'on'. So if there's any perf fallout
from this, targets should look at how they're lowering the uaddo
node in SDAG and/or override that hook.

The x86 diffs suggest that there's some missing pattern-matching
for forming inc/dec.

This should fix the remaining known problems in:
https://bugs.llvm.org/show_bug.cgi?id=40486
https://bugs.llvm.org/show_bug.cgi?id=31754

llvm-svn: 354746
2019-02-24 15:31:27 +00:00

66 lines
1.7 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
; PR31754
; The overflow check may be against the input rather than the sum.
define i1 @uaddo_i64_increment_alt(i64 %x, i64* %p) {
; CHECK-LABEL: uaddo_i64_increment_alt:
; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, #1 // =1
; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret
%a = add i64 %x, 1
store i64 %a, i64* %p
%ov = icmp eq i64 %x, -1
ret i1 %ov
}
; Make sure insertion is done correctly based on dominance.
define i1 @uaddo_i64_increment_alt_dom(i64 %x, i64* %p) {
; CHECK-LABEL: uaddo_i64_increment_alt_dom:
; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, #1 // =1
; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret
%ov = icmp eq i64 %x, -1
%a = add i64 %x, 1
store i64 %a, i64* %p
ret i1 %ov
}
; The overflow check may be against the input rather than the sum.
define i1 @uaddo_i64_decrement_alt(i64 %x, i64* %p) {
; CHECK-LABEL: uaddo_i64_decrement_alt:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, #1 // =1
; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret
%a = add i64 %x, -1
store i64 %a, i64* %p
%ov = icmp ne i64 %x, 0
ret i1 %ov
}
; Make sure insertion is done correctly based on dominance.
define i1 @uaddo_i64_decrement_alt_dom(i64 %x, i64* %p) {
; CHECK-LABEL: uaddo_i64_decrement_alt_dom:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, #1 // =1
; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret
%ov = icmp ne i64 %x, 0
%a = add i64 %x, -1
store i64 %a, i64* %p
ret i1 %ov
}