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49368a63f8
This is essentially finalizes a revert of rL155136,
because nowadays the situation has improved, SCEV can model
all these patterns well, and we canonicalize rotate-like patterns
into a funnel shift intrinsics in InstCombine.
So this should not cause any pessimization.
I've verified the canonicalize-{a,l}shr-shl-to-masking.ll transforms
with alive, which confirms that we can freely preserve exact-ness,
and no-wrap flags.
Profs:
* base: https://rise4fun.com/Alive/gPQ
* exact-ness preservation: https://rise4fun.com/Alive/izi
* nuw preservation: https://rise4fun.com/Alive/DmD
* nsw preservation: https://rise4fun.com/Alive/SLN6N
* nuw nsw preservation: https://rise4fun.com/Alive/Qp7
Refs. https://reviews.llvm.org/D46760
58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine -instcombine-infinite-loop-threshold=2 -S < %s | FileCheck %s
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; <rdar://problem/8606771>
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define i32 @main(i32 %argc) {
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; CHECK-LABEL: @main(
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; CHECK-NEXT: [[T3151:%.*]] = trunc i32 [[ARGC:%.*]] to i8
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; CHECK-NEXT: [[T3163:%.*]] = xor i8 [[T3151]], -1
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; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[T3163]], 5
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; CHECK-NEXT: [[T4127:%.*]] = and i8 [[TMP1]], 64
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; CHECK-NEXT: [[T4086:%.*]] = zext i8 [[T4127]] to i32
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; CHECK-NEXT: ret i32 [[T4086]]
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;
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%t3151 = trunc i32 %argc to i8
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%t3161 = or i8 %t3151, -17
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%t3162 = and i8 %t3151, 122
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%t3163 = xor i8 %t3162, -17
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%t4114 = shl i8 %t3163, 6
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%t4115 = xor i8 %t4114, %t3163
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%t4120 = xor i8 %t3161, %t4115
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%t4126 = lshr i8 %t4120, 7
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%t4127 = mul i8 %t4126, 64
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%t4086 = zext i8 %t4127 to i32
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ret i32 %t4086
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}
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; rdar://8739316
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define i8 @foo(i8 %arg, i8 %arg1) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: [[T:%.*]] = shl i8 [[ARG:%.*]], 7
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; CHECK-NEXT: [[T2:%.*]] = and i8 [[ARG1:%.*]], 84
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; CHECK-NEXT: [[T3:%.*]] = and i8 [[ARG1]], -118
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; CHECK-NEXT: [[T4:%.*]] = and i8 [[ARG1]], 33
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; CHECK-NEXT: [[T5:%.*]] = sub nsw i8 40, [[T2]]
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; CHECK-NEXT: [[T6:%.*]] = and i8 [[T5]], 84
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; CHECK-NEXT: [[T7:%.*]] = or i8 [[T4]], [[T6]]
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; CHECK-NEXT: [[T8:%.*]] = xor i8 [[T]], [[T3]]
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; CHECK-NEXT: [[T9:%.*]] = or i8 [[T7]], [[T8]]
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[T8]], 2
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; CHECK-NEXT: [[T11:%.*]] = and i8 [[TMP1]], 32
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; CHECK-NEXT: [[T12:%.*]] = xor i8 [[T11]], [[T9]]
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; CHECK-NEXT: ret i8 [[T12]]
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;
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%t = shl i8 %arg, 7
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%t2 = and i8 %arg1, 84
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%t3 = and i8 %arg1, -118
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%t4 = and i8 %arg1, 33
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%t5 = sub i8 -88, %t2
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%t6 = and i8 %t5, 84
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%t7 = or i8 %t4, %t6
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%t8 = xor i8 %t, %t3
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%t9 = or i8 %t7, %t8
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%t10 = lshr i8 %t8, 7
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%t11 = shl i8 %t10, 5
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%t12 = xor i8 %t11, %t9
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ret i8 %t12
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}
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