1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
llvm-mirror/test/Transforms/InstCombine/pr43376-getFlippedStrictnessPredicateAndConstant-assert.ll
Bjorn Pettersson bcda8ae597 [InstCombine] Don't assume CmpInst has been visited in getFlippedStrictnessPredicateAndConstant
Summary:
Removing an assumption (assert) that the CmpInst already has been
simplified in getFlippedStrictnessPredicateAndConstant. Solution is
to simply bail out instead of hitting the assertion. Instead we
assume that any profitable rewrite will happen in the next iteration
of InstCombine.

The reason why we can't assume that the CmpInst already has been
simplified is that the worklist does not guarantee such an ordering.

Solves https://bugs.llvm.org/show_bug.cgi?id=43376

Reviewers: spatel, lebedev.ri

Reviewed By: lebedev.ri

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68022

llvm-svn: 372972
2019-09-26 12:16:01 +00:00

37 lines
1.1 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; We used to hit an assertion in getFlippedStrictnessPredicateAndConstant due
; to assuming that edge cases such as %cmp (ult x, 0) already has been
; simplified. But that depends on the worklist order, so that is not always
; guaranteed.
define i16 @d(i16* %d.a, i16* %d.b) {
; CHECK-LABEL: @d(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[T0:%.*]] = load i16, i16* [[D_A:%.*]], align 1
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[T0]], 0
; CHECK-NEXT: br i1 [[TOBOOL]], label [[LAND_END:%.*]], label [[LAND_RHS:%.*]]
; CHECK: land.rhs:
; CHECK-NEXT: br label [[LAND_END]]
; CHECK: land.end:
; CHECK-NEXT: ret i16 -1
;
entry:
%t0 = load i16, i16* %d.a, align 1
%tobool = icmp ne i16 %t0, 0
br i1 %tobool, label %land.rhs, label %land.end
land.rhs:
%t1 = load i16, i16* %d.b, align 1
%cmp = icmp ult i16 %t1, 0
br label %land.end
land.end:
%t2 = phi i1 [ false, %entry ], [ %cmp, %land.rhs ]
%land.ext = zext i1 %t2 to i16
%mul = mul nsw i16 %land.ext, 3
%neg = xor i16 %mul, -1
ret i16 %neg
}