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https://github.com/RPCS3/llvm-mirror.git
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c952d50d89
Fixes https://bugs.llvm.org/show_bug.cgi?id=46680. Just like insertions through IRBuilder, InsertNewInstBefore() should be using the deferred worklist mechanism, so that processing of newly added instructions is prioritized. There's one side-effect of the worklist order change which could be classified as a regression. An add op gets pushed through a select that at the time is not a umax. We could add a reverse transform that tries to push adds in the reverse direction to restore a min/max, but that seems like a sure way of getting infinite loops... Seems like something that should best wait on min/max intrinsics. Differential Revision: https://reviews.llvm.org/D84109
93 lines
3.5 KiB
LLVM
93 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -instcombine -instcombine-infinite-loop-threshold=2 < %s | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-pc-linux-gnu"
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@a = dso_local local_unnamed_addr global i64 0, align 8
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@d = dso_local local_unnamed_addr global i64 0, align 8
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@c = external dso_local local_unnamed_addr global i8, align 1
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define void @test(i16* nocapture readonly %arg) local_unnamed_addr {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[I:%.*]] = load i64, i64* @d, align 8
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; CHECK-NEXT: [[I1:%.*]] = icmp eq i64 [[I]], 0
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; CHECK-NEXT: [[I2:%.*]] = load i64, i64* @a, align 8
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; CHECK-NEXT: [[I3:%.*]] = icmp ne i64 [[I2]], 0
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; CHECK-NEXT: br i1 [[I1]], label [[BB13:%.*]], label [[BB4:%.*]]
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; CHECK: bb4:
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; CHECK-NEXT: [[I5:%.*]] = load i16, i16* [[ARG:%.*]], align 2
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; CHECK-NEXT: [[I6:%.*]] = trunc i16 [[I5]] to i8
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; CHECK-NEXT: store i8 [[I6]], i8* @c, align 1
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[I3]])
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; CHECK-NEXT: br label [[BB22:%.*]]
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; CHECK: bb13:
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; CHECK-NEXT: [[I14:%.*]] = load i16, i16* [[ARG]], align 2
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; CHECK-NEXT: [[I15:%.*]] = trunc i16 [[I14]] to i8
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; CHECK-NEXT: store i8 [[I15]], i8* @c, align 1
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; CHECK-NEXT: br label [[BB22]]
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; CHECK: bb22:
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; CHECK-NEXT: [[STOREMERGE2_IN:%.*]] = load i16, i16* [[ARG]], align 2
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; CHECK-NEXT: [[STOREMERGE2:%.*]] = trunc i16 [[STOREMERGE2_IN]] to i8
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; CHECK-NEXT: store i8 [[STOREMERGE2]], i8* @c, align 1
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; CHECK-NEXT: [[STOREMERGE1_IN:%.*]] = load i16, i16* [[ARG]], align 2
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; CHECK-NEXT: [[STOREMERGE1:%.*]] = trunc i16 [[STOREMERGE1_IN]] to i8
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; CHECK-NEXT: store i8 [[STOREMERGE1]], i8* @c, align 1
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; CHECK-NEXT: [[STOREMERGE_IN:%.*]] = load i16, i16* [[ARG]], align 2
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; CHECK-NEXT: [[STOREMERGE:%.*]] = trunc i16 [[STOREMERGE_IN]] to i8
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; CHECK-NEXT: store i8 [[STOREMERGE]], i8* @c, align 1
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; CHECK-NEXT: br label [[BB23:%.*]]
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; CHECK: bb23:
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; CHECK-NEXT: br label [[BB23]]
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;
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bb:
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%i = load i64, i64* @d, align 8
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%i1 = icmp eq i64 %i, 0
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%i2 = load i64, i64* @a, align 8
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%i3 = icmp ne i64 %i2, 0
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br i1 %i1, label %bb13, label %bb4
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bb4: ; preds = %bb
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%i5 = load i16, i16* %arg, align 2
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%i6 = trunc i16 %i5 to i8
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store i8 %i6, i8* @c, align 1
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tail call void @llvm.assume(i1 %i3)
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%i7 = load i16, i16* %arg, align 2
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%i8 = trunc i16 %i7 to i8
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store i8 %i8, i8* @c, align 1
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%i9 = load i16, i16* %arg, align 2
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%i10 = trunc i16 %i9 to i8
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store i8 %i10, i8* @c, align 1
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%i11 = load i16, i16* %arg, align 2
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%i12 = trunc i16 %i11 to i8
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store i8 %i12, i8* @c, align 1
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br label %bb22
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bb13: ; preds = %bb
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%i14 = load i16, i16* %arg, align 2
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%i15 = trunc i16 %i14 to i8
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store i8 %i15, i8* @c, align 1
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%i16 = load i16, i16* %arg, align 2
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%i17 = trunc i16 %i16 to i8
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store i8 %i17, i8* @c, align 1
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%i18 = load i16, i16* %arg, align 2
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%i19 = trunc i16 %i18 to i8
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store i8 %i19, i8* @c, align 1
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%i20 = load i16, i16* %arg, align 2
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%i21 = trunc i16 %i20 to i8
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store i8 %i21, i8* @c, align 1
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br label %bb22
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bb22: ; preds = %bb13, %bb4
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br label %bb23
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bb23: ; preds = %bb23, %bb22
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br label %bb23
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}
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; Function Attrs: nounwind willreturn
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declare void @llvm.assume(i1) #0
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attributes #0 = { nounwind willreturn }
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