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79615641f1
construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. llvm-svn: 79719
9 lines
276 B
LLVM
9 lines
276 B
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=-neon
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; Example that requires splitting and expanding a vector shift.
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define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
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entry:
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%shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %shr
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}
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