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3633380341
Summary: In SelectionDAG, when a store is immediately chained to another store to the same address, elide the first store as it has no observable effects. This is causes small improvements dealing with intrinsics lowered to stores. Test notes: * Many testcases overwrite store addresses multiple times and needed minor changes, mainly making stores volatile to prevent the optimization from optimizing the test away. * Many X86 test cases optimized out instructions associated with associated with va_start. * Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has dependencies to check and can probably be removed and potentially replaced with another test. Reviewers: rnk, john.brawn Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33206 llvm-svn: 303198
77 lines
3.3 KiB
LLVM
77 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-atomic-cfg-tidy=0 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
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; rdar://7352504
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; Make sure we use "str r9, [sp, #+28]" instead of "sub.w r4, r7, #256" followed by "str r9, [r4, #-32]".
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%0 = type { i16, i8, i8 }
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%1 = type { [2 x i32], [2 x i32] }
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%2 = type { %union.rec* }
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%struct.FILE_POS = type { i8, i8, i16, i32 }
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%struct.GAP = type { i8, i8, i16 }
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%struct.LIST = type { %union.rec*, %union.rec* }
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%struct.STYLE = type { %union.anon, %union.anon, i16, i16, i32 }
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%struct.head_type = type { [2 x %struct.LIST], %union.FIRST_UNION, %union.SECOND_UNION, %union.THIRD_UNION, %union.FOURTH_UNION, %union.rec*, %2, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, i32 }
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%union.FIRST_UNION = type { %struct.FILE_POS }
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%union.FOURTH_UNION = type { %struct.STYLE }
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%union.SECOND_UNION = type { %0 }
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%union.THIRD_UNION = type { %1 }
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%union.anon = type { %struct.GAP }
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%union.rec = type { %struct.head_type }
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@zz_hold = external global %union.rec* ; <%union.rec**> [#uses=2]
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@zz_res = external global %union.rec* ; <%union.rec**> [#uses=1]
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define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
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entry:
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; CHECK: ldr{{(.w)?}} {{(r[0-9]+)|(lr)}}, [r7, #28]
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%xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
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%ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
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br label %bb20
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bb20: ; preds = %entry
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switch i32 undef, label %bb1287 [
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i32 110, label %bb119
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i32 120, label %bb119
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i32 210, label %bb420
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i32 230, label %bb420
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i32 450, label %bb438
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i32 460, label %bb438
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i32 550, label %bb533
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i32 560, label %bb569
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i32 640, label %bb745
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i32 780, label %bb1098
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]
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bb119: ; preds = %bb20, %bb20
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unreachable
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bb420: ; preds = %bb20, %bb20
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; CHECK: bb420
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; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp
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; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp
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; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp
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; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp
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store volatile %union.rec* null, %union.rec** @zz_hold, align 4
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store %union.rec* null, %union.rec** @zz_res, align 4
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store volatile %union.rec* %x, %union.rec** @zz_hold, align 4
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%0 = call %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0]
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unreachable
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bb438: ; preds = %bb20, %bb20
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unreachable
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bb533: ; preds = %bb20
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ret %union.rec* %x
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bb569: ; preds = %bb20
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unreachable
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bb745: ; preds = %bb20
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unreachable
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bb1098: ; preds = %bb20
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unreachable
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bb1287: ; preds = %bb20
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unreachable
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}
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