Rafael Espindola b1ae74bd73 Fix another case where we were preferring instructions with large ... immediates instead of 8 bits ones. llvm-svn: 116410		2010-10-13 17:14:25 +00:00
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Alpha
ARM	Found a bug turning this on by default. Disable again for now.	2010-10-11 20:26:21 +00:00
Blackfin
CBackend
CellSPU	Zap some redundant 'ori $?, $?, 0' from SPU.	2010-10-01 09:20:01 +00:00
CPP
Generic
MBlaze
Mips	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
MSP430	CombinerAA is now reordering these stores.	2010-09-20 20:56:29 +00:00
PowerPC	PowerPC varargs functions store live-in registers on the stack. Make sure we use	2010-10-11 20:43:09 +00:00
PTX	Add test case for PTX ret instruction	2010-09-25 07:49:54 +00:00
SPARC
SystemZ
Thumb	Try again to disable critical edge splitting in CodeGenPrepare.	2010-09-30 20:51:52 +00:00
Thumb2	Change register allocation order for ARM VFP and NEON registers to put the	2010-10-08 06:15:13 +00:00
X86	Fix another case where we were preferring instructions with large	2010-10-13 17:14:25 +00:00
XCore	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
thumb2-mul.ll	Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes	2010-09-21 22:51:46 +00:00