Bruno Cardoso Lopes bf95b9699e - Add sugregister logic to handle f64=(f32,f32). ... - Support mips1 like load/store of doubles: Instead of: sdc $f0, X($3) Generate: swc $f0, X($3) swc $f1, X+4($3) llvm-svn: 89322		2009-11-19 06:06:13 +00:00
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Alpha
ARM	Fix buildbots.	2009-11-18 23:30:38 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic	Added a testcase for PR5495.	2009-11-16 20:03:13 +00:00
Mips	- Add sugregister logic to handle f64=(f32,f32).	2009-11-19 06:06:13 +00:00
MSP430
PIC16
PowerPC
SPARC
SystemZ
Thumb
Thumb2	Enable arm jumpt table adjustment.	2009-11-17 21:24:11 +00:00
X86	Test from Dhrystone to make sure that we're not emitting an aligned load for a	2009-11-19 01:33:57 +00:00
XCore	Add XCore support for indirectbr / blockaddress.	2009-11-18 23:20:42 +00:00