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Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
17 lines
611 B
TableGen
17 lines
611 B
TableGen
//===-- AMDGPUIntrinsics.td - Common intrinsics -*- tablegen -*-----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines intrinsics that are used by all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "AMDGPU", isTarget = 1 in {
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def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
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}
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