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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
12 lines
306 B
LLVM
12 lines
306 B
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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define float @fcvtxn(double %a) {
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; CHECK-LABEL: fcvtxn:
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; CHECK: fcvtxn s0, d0
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; CHECK-NEXT: ret
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%vcvtxd.i = tail call float @llvm.arm64.sisd.fcvtxn(double %a) nounwind
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ret float %vcvtxd.i
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}
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declare float @llvm.arm64.sisd.fcvtxn(double) nounwind readnone
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