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432 lines
13 KiB
C++
432 lines
13 KiB
C++
//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86 specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86CallLowering.h"
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#include "X86LegalizerInfo.h"
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#include "X86RegisterBankInfo.h"
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#include "X86Subtarget.h"
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86TargetMachine.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/ConstantRange.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#if defined(_MSC_VER)
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#include <intrin.h>
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#endif
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using namespace llvm;
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#define DEBUG_TYPE "subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "X86GenSubtargetInfo.inc"
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// Temporary option to control early if-conversion for x86 while adding machine
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// models.
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static cl::opt<bool>
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X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
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cl::desc("Enable early if-conversion on X86"));
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/// Classify a blockaddress reference for the current subtarget according to how
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/// we should reference it in a non-pcrel context.
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unsigned char X86Subtarget::classifyBlockAddressReference() const {
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return classifyLocalReference(nullptr);
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}
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/// Classify a global variable reference for the current subtarget according to
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/// how we should reference it in a non-pcrel context.
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unsigned char
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X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const {
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return classifyGlobalReference(GV, *GV->getParent());
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}
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unsigned char
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X86Subtarget::classifyLocalReference(const GlobalValue *GV) const {
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// 64 bits can use %rip addressing for anything local.
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if (is64Bit())
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return X86II::MO_NO_FLAG;
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// If this is for a position dependent executable, the static linker can
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// figure it out.
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if (!isPositionIndependent())
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return X86II::MO_NO_FLAG;
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// The COFF dynamic linker just patches the executable sections.
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if (isTargetCOFF())
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return X86II::MO_NO_FLAG;
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if (isTargetDarwin()) {
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// 32 bit macho has no relocation for a-b if a is undefined, even if
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// b is in the section that is being relocated.
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// This means we have to use o load even for GVs that are known to be
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// local to the dso.
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if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
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return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
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return X86II::MO_PIC_BASE_OFFSET;
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}
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return X86II::MO_GOTOFF;
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}
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unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV,
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const Module &M) const {
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// Large model never uses stubs.
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if (TM.getCodeModel() == CodeModel::Large)
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return X86II::MO_NO_FLAG;
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// Absolute symbols can be referenced directly.
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if (GV) {
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if (Optional<ConstantRange> CR = GV->getAbsoluteSymbolRange()) {
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// See if we can use the 8-bit immediate form. Note that some instructions
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// will sign extend the immediate operand, so to be conservative we only
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// accept the range [0,128).
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if (CR->getUnsignedMax().ult(128))
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return X86II::MO_ABS8;
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else
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return X86II::MO_NO_FLAG;
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}
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}
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if (TM.shouldAssumeDSOLocal(M, GV))
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return classifyLocalReference(GV);
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if (isTargetCOFF())
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return X86II::MO_DLLIMPORT;
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if (is64Bit())
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return X86II::MO_GOTPCREL;
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if (isTargetDarwin()) {
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if (!isPositionIndependent())
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return X86II::MO_DARWIN_NONLAZY;
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return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
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}
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return X86II::MO_GOT;
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}
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unsigned char
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X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
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return classifyGlobalFunctionReference(GV, *GV->getParent());
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}
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unsigned char
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X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
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const Module &M) const {
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if (TM.shouldAssumeDSOLocal(M, GV))
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return X86II::MO_NO_FLAG;
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if (isTargetCOFF()) {
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assert(GV->hasDLLImportStorageClass() &&
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"shouldAssumeDSOLocal gave inconsistent answer");
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return X86II::MO_DLLIMPORT;
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}
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const Function *F = dyn_cast_or_null<Function>(GV);
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if (isTargetELF()) {
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if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
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// According to psABI, PLT stub clobbers XMM8-XMM15.
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// In Regcall calling convention those registers are used for passing
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// parameters. Thus we need to prevent lazy binding in Regcall.
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return X86II::MO_GOTPCREL;
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// If PLT must be avoided then the call should be via GOTPCREL.
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if (((F && F->hasFnAttribute(Attribute::NonLazyBind)) ||
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(!F && M.getRtLibUseGOT())) &&
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is64Bit())
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return X86II::MO_GOTPCREL;
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return X86II::MO_PLT;
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}
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if (is64Bit()) {
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if (F && F->hasFnAttribute(Attribute::NonLazyBind))
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// If the function is marked as non-lazy, generate an indirect call
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// which loads from the GOT directly. This avoids runtime overhead
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// at the cost of eager binding (and one extra byte of encoding).
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return X86II::MO_GOTPCREL;
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return X86II::MO_NO_FLAG;
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}
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return X86II::MO_NO_FLAG;
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}
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/// Return true if the subtarget allows calls to immediate address.
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bool X86Subtarget::isLegalToCallImmediateAddr() const {
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// FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
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// but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
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// the following check for Win32 should be removed.
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if (In64BitMode || isTargetWin32())
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return false;
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return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
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}
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void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "generic";
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// Make sure 64-bit features are available in 64-bit mode. (But make sure
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// SSE2 can be turned off explicitly.)
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std::string FullFS = FS;
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if (In64BitMode) {
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if (!FullFS.empty())
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FullFS = "+64bit,+sse2," + FullFS;
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else
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FullFS = "+64bit,+sse2";
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}
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// LAHF/SAHF are always supported in non-64-bit mode.
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if (!In64BitMode) {
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if (!FullFS.empty())
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FullFS = "+sahf," + FullFS;
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else
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FullFS = "+sahf";
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}
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// Parse features string and set the CPU.
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ParseSubtargetFeatures(CPUName, FullFS);
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// All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
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// 16-bytes and under that are reasonably fast. These features were
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// introduced with Intel's Nehalem/Silvermont and AMD's Family10h
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// micro-architectures respectively.
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if (hasSSE42() || hasSSE4A())
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IsUAMem16Slow = false;
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InstrItins = getInstrItineraryForCPU(CPUName);
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// It's important to keep the MCSubtargetInfo feature bits in sync with
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// target data structure which is shared with MC code emitter, etc.
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if (In64BitMode)
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ToggleFeature(X86::Mode64Bit);
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else if (In32BitMode)
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ToggleFeature(X86::Mode32Bit);
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else if (In16BitMode)
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ToggleFeature(X86::Mode16Bit);
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else
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llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
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DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
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<< ", 3DNowLevel " << X863DNowLevel
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<< ", 64bit " << HasX86_64 << "\n");
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assert((!In64BitMode || HasX86_64) &&
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"64-bit code requested on a subtarget that doesn't support it!");
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// Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
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// 32 and 64 bit) and for all 64-bit targets.
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if (StackAlignOverride)
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stackAlignment = StackAlignOverride;
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else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
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isTargetKFreeBSD() || In64BitMode)
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stackAlignment = 16;
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// Some CPUs have more overhead for gather. The specified overhead is relative
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// to the Load operation. "2" is the number provided by Intel architects. This
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// parameter is used for cost estimation of Gather Op and comparison with
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// other alternatives.
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// TODO: Remove the explicit hasAVX512()?, That would mean we would only
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// enable gather with a -march.
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if (hasAVX512() || (hasAVX2() && hasFastGather()))
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GatherOverhead = 2;
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if (hasAVX512())
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ScatterOverhead = 2;
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// Consume the vector width attribute or apply any target specific limit.
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if (PreferVectorWidthOverride)
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PreferVectorWidth = PreferVectorWidthOverride;
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else if (Prefer256Bit)
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PreferVectorWidth = 256;
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}
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void X86Subtarget::initializeEnvironment() {
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X86SSELevel = NoSSE;
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X863DNowLevel = NoThreeDNow;
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HasX87 = false;
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HasNOPL = false;
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HasCMov = false;
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HasX86_64 = false;
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HasPOPCNT = false;
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HasSSE4A = false;
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HasAES = false;
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HasVAES = false;
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HasFXSR = false;
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HasXSAVE = false;
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HasXSAVEOPT = false;
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HasXSAVEC = false;
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HasXSAVES = false;
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HasPCLMUL = false;
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HasVPCLMULQDQ = false;
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HasGFNI = false;
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HasFMA = false;
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HasFMA4 = false;
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HasXOP = false;
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HasTBM = false;
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HasLWP = false;
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HasMOVBE = false;
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HasRDRAND = false;
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HasF16C = false;
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HasFSGSBase = false;
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HasLZCNT = false;
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HasBMI = false;
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HasBMI2 = false;
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HasVBMI = false;
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HasVBMI2 = false;
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HasIFMA = false;
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HasRTM = false;
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HasERI = false;
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HasCDI = false;
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HasPFI = false;
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HasDQI = false;
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HasVPOPCNTDQ = false;
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HasBWI = false;
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HasVLX = false;
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HasADX = false;
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HasPKU = false;
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HasVNNI = false;
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HasBITALG = false;
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HasSHA = false;
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HasPREFETCHWT1 = false;
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HasPRFCHW = false;
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HasRDSEED = false;
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HasLAHFSAHF = false;
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HasMWAITX = false;
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HasCLZERO = false;
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HasMPX = false;
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HasSHSTK = false;
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HasIBT = false;
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HasSGX = false;
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HasCLFLUSHOPT = false;
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HasCLWB = false;
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HasRDPID = false;
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UseRetpoline = false;
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UseRetpolineExternalThunk = false;
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IsPMULLDSlow = false;
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IsSHLDSlow = false;
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IsUAMem16Slow = false;
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IsUAMem32Slow = false;
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HasSSEUnalignedMem = false;
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HasCmpxchg16b = false;
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UseLeaForSP = false;
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HasPOPCNTFalseDeps = false;
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HasLZCNTFalseDeps = false;
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HasFastVariableShuffle = false;
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HasFastPartialYMMorZMMWrite = false;
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HasFast11ByteNOP = false;
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HasFast15ByteNOP = false;
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HasFastGather = false;
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HasFastScalarFSQRT = false;
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HasFastVectorFSQRT = false;
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HasFastLZCNT = false;
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HasFastSHLDRotate = false;
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HasMacroFusion = false;
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HasERMSB = false;
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HasSlowDivide32 = false;
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HasSlowDivide64 = false;
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PadShortFunctions = false;
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SlowTwoMemOps = false;
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LEAUsesAG = false;
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SlowLEA = false;
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Slow3OpsLEA = false;
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SlowIncDec = false;
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stackAlignment = 4;
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// FIXME: this is a known good value for Yonah. How about others?
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MaxInlineSizeThreshold = 128;
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UseSoftFloat = false;
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X86ProcFamily = Others;
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GatherOverhead = 1024;
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ScatterOverhead = 1024;
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PreferVectorWidth = UINT32_MAX;
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Prefer256Bit = false;
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}
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X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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initializeEnvironment();
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initSubtargetFeatures(CPU, FS);
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return *this;
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}
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X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const X86TargetMachine &TM,
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unsigned StackAlignOverride,
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unsigned PreferVectorWidthOverride,
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unsigned RequiredVectorWidth)
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: X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
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PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
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StackAlignOverride(StackAlignOverride),
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PreferVectorWidthOverride(PreferVectorWidthOverride),
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RequiredVectorWidth(RequiredVectorWidth),
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In64BitMode(TargetTriple.getArch() == Triple::x86_64),
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In32BitMode(TargetTriple.getArch() == Triple::x86 &&
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TargetTriple.getEnvironment() != Triple::CODE16),
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In16BitMode(TargetTriple.getArch() == Triple::x86 &&
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TargetTriple.getEnvironment() == Triple::CODE16),
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InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
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FrameLowering(*this, getStackAlignment()) {
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// Determine the PICStyle based on the target selected.
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if (!isPositionIndependent())
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setPICStyle(PICStyles::None);
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else if (is64Bit())
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setPICStyle(PICStyles::RIPRel);
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else if (isTargetCOFF())
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setPICStyle(PICStyles::None);
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else if (isTargetDarwin())
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setPICStyle(PICStyles::StubPIC);
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else if (isTargetELF())
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setPICStyle(PICStyles::GOT);
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CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
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Legalizer.reset(new X86LegalizerInfo(*this, TM));
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auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
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RegBankInfo.reset(RBI);
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InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
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}
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const CallLowering *X86Subtarget::getCallLowering() const {
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return CallLoweringInfo.get();
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}
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const InstructionSelector *X86Subtarget::getInstructionSelector() const {
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return InstSelector.get();
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}
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const LegalizerInfo *X86Subtarget::getLegalizerInfo() const {
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return Legalizer.get();
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}
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const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
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return RegBankInfo.get();
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}
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bool X86Subtarget::enableEarlyIfConversion() const {
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return hasCMov() && X86EarlyIfConv;
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}
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