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bfeca81c05
Prevent producing real strange tablegen code by using proper register sizes, alignments and hierarchy. Also cleanup the unused definitions and add some comments. v2: add SGPR 512 bit registers, stop registers from wrapping around, fix SGPR alignment This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176098 |
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Analysis | ||
Archive | ||
AsmParser | ||
Bitcode | ||
CodeGen | ||
DebugInfo | ||
ExecutionEngine | ||
IR | ||
Linker | ||
MC | ||
Object | ||
Option | ||
Support | ||
TableGen | ||
Target | ||
Transforms | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile |