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c00f228e84
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 313960
53 lines
1.5 KiB
TableGen
53 lines
1.5 KiB
TableGen
//===-- BPFRegisterInfo.td - BPF Register defs -------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the BPF register file
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//===----------------------------------------------------------------------===//
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let Namespace = "BPF" in {
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def sub_32 : SubRegIndex<32>;
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}
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class Wi<bits<16> Enc, string n> : Register<n> {
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let HWEncoding = Enc;
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let Namespace = "BPF";
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}
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// Registers are identified with 4-bit ID numbers.
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// Ri - 64-bit integer registers
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class Ri<bits<16> Enc, string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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let HWEncoding = Enc;
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let Namespace = "BPF";
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let SubRegIndices = [sub_32];
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}
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foreach I = 0-11 in {
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// 32-bit Integer (alias to low part of 64-bit register).
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def W#I : Wi<I, "w"#I>, DwarfRegNum<[I]>;
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// 64-bit Integer registers
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def R#I : Ri<I, "r"#I, [!cast<Wi>("W"#I)]>, DwarfRegNum<[I]>;
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}
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// Register classes.
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def GPR32 : RegisterClass<"BPF", [i32], 32, (add
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(sequence "W%u", 1, 9),
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W0, // Return value
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W11, // Stack Ptr
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W10 // Frame Ptr
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)>;
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def GPR : RegisterClass<"BPF", [i64], 64, (add
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(sequence "R%u", 1, 9),
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R0, // Return value
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R11, // Stack Ptr
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R10 // Frame Ptr
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)>;
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