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12536f21d1
The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
9 lines
257 B
LLVM
9 lines
257 B
LLVM
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
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; PR4091
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define void @foo(i32 %i, i32* %p) nounwind {
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;CHECK: swp r2, r0, [r1]
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%asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(i32* %p, i32 %i, i32* %p) nounwind
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ret void
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}
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