1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
llvm-mirror/test/CodeGen/X86/2009-03-09-SpillerBug.ll
Dan Gohman 5f6f8101d5 Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
2009-06-04 22:49:04 +00:00

19 lines
685 B
LLVM

; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu
; PR3706
define void @__mulxc3(x86_fp80 %b) nounwind {
entry:
%call = call x86_fp80 @y(x86_fp80* null, x86_fp80* null) ; <x86_fp80> [#uses=0]
%cmp = fcmp ord x86_fp80 %b, 0xK00000000000000000000 ; <i1> [#uses=1]
%sub = fsub x86_fp80 %b, %b ; <x86_fp80> [#uses=1]
%cmp7 = fcmp uno x86_fp80 %sub, 0xK00000000000000000000 ; <i1> [#uses=1]
%and12 = and i1 %cmp7, %cmp ; <i1> [#uses=1]
%and = zext i1 %and12 to i32 ; <i32> [#uses=1]
%conv9 = sitofp i32 %and to x86_fp80 ; <x86_fp80> [#uses=1]
store x86_fp80 %conv9, x86_fp80* null
store x86_fp80 %b, x86_fp80* null
ret void
}
declare x86_fp80 @y(x86_fp80*, x86_fp80*)