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https://github.com/RPCS3/llvm-mirror.git
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aa4e725a3a
Reintroduce r245442. Remove an overly conservative assertion introduced in r245442. We could replace the assertion to use `shareSameRegisterFile` instead, but in that point in `insertPHI` we already lost the original Def subreg to check against. So drop the assertion completely. Original commit message: - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 245479
85 lines
2.9 KiB
LLVM
85 lines
2.9 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s
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%SA = type <{ %union.anon, i32, [4 x i8], i8*, i8*, i8*, i32, [4 x i8] }>
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%union.anon = type { <1 x i64> }
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; Check that extra movd (copy) instructions aren't generated.
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define i32 @test(%SA* %pSA, i16* %A, i32 %B, i32 %C, i32 %D, i8* %E) {
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entry:
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; CHECK-LABEL: test
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; CHECK: # BB#0:
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; CHECK-NEXT: pshufw
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; CHECK-NEXT: movd
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; CHECK-NOT: movd
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; CHECK-NEXT: testl
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%shl = shl i32 1, %B
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%shl1 = shl i32 %C, %B
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%shl2 = shl i32 1, %D
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%v = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 0, i32 0
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%v0 = load <1 x i64>, <1 x i64>* %v, align 8
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%SA0 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 1
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%v1 = load i32, i32* %SA0, align 4
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%SA1 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 3
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%v2 = load i8*, i8** %SA1, align 8
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%SA2 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 4
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%v3 = load i8*, i8** %SA2, align 8
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%v4 = bitcast <1 x i64> %v0 to <4 x i16>
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%v5 = bitcast <4 x i16> %v4 to x86_mmx
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%v6 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v5, i8 -18)
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%v7 = bitcast x86_mmx %v6 to <4 x i16>
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%v8 = bitcast <4 x i16> %v7 to <1 x i64>
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%v9 = extractelement <1 x i64> %v8, i32 0
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%v10 = bitcast i64 %v9 to <2 x i32>
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%v11 = extractelement <2 x i32> %v10, i32 0
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%cmp = icmp eq i32 %v11, 0
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br i1 %cmp, label %if.A, label %if.B
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if.A:
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; CHECK: %if.A
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; CHECK-NEXT: movd
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; CHECK-NEXT: psllq
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%pa = phi <1 x i64> [ %v8, %entry ], [ %vx, %if.C ]
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%v17 = extractelement <1 x i64> %pa, i32 0
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%v18 = bitcast i64 %v17 to x86_mmx
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%v19 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %v18, i32 %B) #2
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%v20 = bitcast x86_mmx %v19 to i64
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%v21 = insertelement <1 x i64> undef, i64 %v20, i32 0
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%cmp3 = icmp eq i64 %v20, 0
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br i1 %cmp3, label %if.C, label %merge
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if.B:
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%v34 = bitcast <1 x i64> %v8 to <4 x i16>
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%v35 = bitcast <4 x i16> %v34 to x86_mmx
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%v36 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v35, i8 -18)
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%v37 = bitcast x86_mmx %v36 to <4 x i16>
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%v38 = bitcast <4 x i16> %v37 to <1 x i64>
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br label %if.C
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if.C:
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%vx = phi <1 x i64> [ %v21, %if.A ], [ %v38, %if.B ]
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%cvt = bitcast <1 x i64> %vx to <2 x i32>
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%ex = extractelement <2 x i32> %cvt, i32 0
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%cmp2 = icmp eq i32 %ex, 0
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br i1 %cmp2, label %if.A, label %merge
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merge:
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; CHECK: %merge
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; CHECK-NOT: movd
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; CHECK-NEXT: pshufw
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%vy = phi <1 x i64> [ %v21, %if.A ], [ %vx, %if.C ]
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%v130 = bitcast <1 x i64> %vy to <4 x i16>
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%v131 = bitcast <4 x i16> %v130 to x86_mmx
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%v132 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v131, i8 -18)
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%v133 = bitcast x86_mmx %v132 to <4 x i16>
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%v134 = bitcast <4 x i16> %v133 to <1 x i64>
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%v135 = extractelement <1 x i64> %v134, i32 0
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%v136 = bitcast i64 %v135 to <2 x i32>
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%v137 = extractelement <2 x i32> %v136, i32 0
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ret i32 %v137
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}
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declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
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declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
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