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c3f1114c60
Relanding after rewriting undef.ll test to avoid host-dependant
endianness.
As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using
generic checks. Also, propagate missing local handling from there to
BaseIndexOffset checks.
Tests of note:
* test/CodeGen/X86/build-vector* - Improved.
* test/CodeGen/BPF/undef.ll - Improved store alignment allows an
additional store merge
* test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a
case we already do not handle well. Here, the DAG is improved, but
scheduling causes a code size degradation.
Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab
Subscribers: nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D34472
llvm-svn: 307114
70 lines
1.6 KiB
LLVM
70 lines
1.6 KiB
LLVM
; RUN: llc -march=msp430 < %s | FileCheck %s
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target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
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target triple = "msp430-generic-generic"
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@foo = common global i16 0, align 2
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@bar = common global i16 0, align 2
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define void @mov() nounwind {
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; CHECK-LABEL: mov:
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; CHECK: mov.w &bar, &foo
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%1 = load i16, i16* @bar
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store i16 %1, i16* @foo
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ret void
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}
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define void @add() nounwind {
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; CHECK-LABEL: add:
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; CHECK: add.w &bar, &foo
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%1 = load i16, i16* @bar
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%2 = load i16, i16* @foo
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%3 = add i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @and() nounwind {
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; CHECK-LABEL: and:
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; CHECK: and.w &bar, &foo
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%1 = load i16, i16* @bar
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%2 = load i16, i16* @foo
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%3 = and i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @bis() nounwind {
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; CHECK-LABEL: bis:
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; CHECK: bis.w &bar, &foo
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%1 = load i16, i16* @bar
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%2 = load i16, i16* @foo
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%3 = or i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @xor() nounwind {
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; CHECK-LABEL: xor:
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; CHECK: xor.w &bar, &foo
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%1 = load i16, i16* @bar
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%2 = load i16, i16* @foo
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%3 = xor i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define i16 @mov2() nounwind {
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entry:
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%retval = alloca i16 ; <i16*> [#uses=3]
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%x = alloca i32, align 2 ; <i32*> [#uses=1]
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%y = alloca i32, align 2 ; <i32*> [#uses=1]
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store i16 0, i16* %retval
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%tmp = load i32, i32* %y ; <i32> [#uses=1]
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store i32 %tmp, i32* %x
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store i16 0, i16* %retval
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%0 = load i16, i16* %retval ; <i16> [#uses=1]
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ret i16 %0
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; CHECK-LABEL: mov2:
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; CHECK-DAG: mov.w 2(r1), 6(r1)
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; CHECK-DAG: mov.w 0(r1), 4(r1)
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}
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