mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
ae65e281f3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
55 lines
2.0 KiB
C++
55 lines
2.0 KiB
C++
//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements an allocation order for virtual registers.
|
|
//
|
|
// The preferred allocation order for a virtual register depends on allocation
|
|
// hints and target hooks. The AllocationOrder class encapsulates all of that.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "AllocationOrder.h"
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
#include "llvm/CodeGen/RegisterClassInfo.h"
|
|
#include "llvm/CodeGen/VirtRegMap.h"
|
|
#include "llvm/Support/Debug.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
|
|
using namespace llvm;
|
|
|
|
#define DEBUG_TYPE "regalloc"
|
|
|
|
// Compare VirtRegMap::getRegAllocPref().
|
|
AllocationOrder::AllocationOrder(unsigned VirtReg,
|
|
const VirtRegMap &VRM,
|
|
const RegisterClassInfo &RegClassInfo,
|
|
const LiveRegMatrix *Matrix)
|
|
: Pos(0), HardHints(false) {
|
|
const MachineFunction &MF = VRM.getMachineFunction();
|
|
const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
|
|
Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
|
|
if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
|
|
HardHints = true;
|
|
rewind();
|
|
|
|
LLVM_DEBUG({
|
|
if (!Hints.empty()) {
|
|
dbgs() << "hints:";
|
|
for (unsigned I = 0, E = Hints.size(); I != E; ++I)
|
|
dbgs() << ' ' << printReg(Hints[I], TRI);
|
|
dbgs() << '\n';
|
|
}
|
|
});
|
|
#ifndef NDEBUG
|
|
for (unsigned I = 0, E = Hints.size(); I != E; ++I)
|
|
assert(is_contained(Order, Hints[I]) &&
|
|
"Target hint is outside allocation order.");
|
|
#endif
|
|
}
|