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604077c19d
isPrefix was added to support the patches to align branches. it relies on a switch over instruction names. This moves those opcodes to a new format so the information is tablegen and we can just check for a specific value in some bits in TSFlags instead. I've left the other function in place for now so that the existing patches in phabricator will still work. I'll work with the owner to get them migrated.
359 lines
14 KiB
C++
359 lines
14 KiB
C++
//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler Emitter.
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// It contains the interface of a single recognizable instruction.
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// Documentation for the disassembler emitter in general can be found in
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// X86DisassemblerEmitter.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
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#define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
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#include "CodeGenTarget.h"
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#include "X86DisassemblerTables.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/TableGen/Record.h"
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namespace llvm {
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#define X86_INSTR_MRM_MAPPING \
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MAP(C0, 64) \
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MAP(C1, 65) \
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MAP(C2, 66) \
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MAP(C3, 67) \
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MAP(C4, 68) \
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MAP(C5, 69) \
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MAP(C6, 70) \
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MAP(C7, 71) \
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MAP(C8, 72) \
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MAP(C9, 73) \
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MAP(CA, 74) \
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MAP(CB, 75) \
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MAP(CC, 76) \
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MAP(CD, 77) \
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MAP(CE, 78) \
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MAP(CF, 79) \
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MAP(D0, 80) \
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MAP(D1, 81) \
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MAP(D2, 82) \
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MAP(D3, 83) \
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MAP(D4, 84) \
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MAP(D5, 85) \
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MAP(D6, 86) \
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MAP(D7, 87) \
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MAP(D8, 88) \
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MAP(D9, 89) \
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MAP(DA, 90) \
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MAP(DB, 91) \
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MAP(DC, 92) \
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MAP(DD, 93) \
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MAP(DE, 94) \
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MAP(DF, 95) \
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MAP(E0, 96) \
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MAP(E1, 97) \
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MAP(E2, 98) \
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MAP(E3, 99) \
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MAP(E4, 100) \
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MAP(E5, 101) \
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MAP(E6, 102) \
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MAP(E7, 103) \
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MAP(E8, 104) \
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MAP(E9, 105) \
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MAP(EA, 106) \
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MAP(EB, 107) \
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MAP(EC, 108) \
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MAP(ED, 109) \
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MAP(EE, 110) \
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MAP(EF, 111) \
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MAP(F0, 112) \
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MAP(F1, 113) \
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MAP(F2, 114) \
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MAP(F3, 115) \
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MAP(F4, 116) \
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MAP(F5, 117) \
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MAP(F6, 118) \
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MAP(F7, 119) \
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MAP(F8, 120) \
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MAP(F9, 121) \
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MAP(FA, 122) \
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MAP(FB, 123) \
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MAP(FC, 124) \
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MAP(FD, 125) \
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MAP(FE, 126) \
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MAP(FF, 127)
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// A clone of X86 since we can't depend on something that is generated.
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namespace X86Local {
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enum {
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Pseudo = 0,
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RawFrm = 1,
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AddRegFrm = 2,
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RawFrmMemOffs = 3,
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RawFrmSrc = 4,
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RawFrmDst = 5,
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RawFrmDstSrc = 6,
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RawFrmImm8 = 7,
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RawFrmImm16 = 8,
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AddCCFrm = 9,
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PrefixByte = 10,
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MRMDestMem = 32,
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MRMSrcMem = 33,
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MRMSrcMem4VOp3 = 34,
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MRMSrcMemOp4 = 35,
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MRMSrcMemCC = 36,
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MRMXmCC = 38, MRMXm = 39,
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MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43,
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MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47,
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MRMDestReg = 48,
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MRMSrcReg = 49,
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MRMSrcReg4VOp3 = 50,
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MRMSrcRegOp4 = 51,
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MRMSrcRegCC = 52,
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MRMXrCC = 54, MRMXr = 55,
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MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59,
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MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63,
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#define MAP(from, to) MRM_##from = to,
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X86_INSTR_MRM_MAPPING
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#undef MAP
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};
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enum {
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OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7
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};
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enum {
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PD = 1, XS = 2, XD = 3, PS = 4
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};
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enum {
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VEX = 1, XOP = 2, EVEX = 3
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};
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enum {
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OpSize16 = 1, OpSize32 = 2
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};
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enum {
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AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
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};
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}
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namespace X86Disassembler {
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/// RecognizableInstr - Encapsulates all information required to decode a single
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/// instruction, as extracted from the LLVM instruction tables. Has methods
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/// to interpret the information available in the LLVM tables, and to emit the
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/// instruction into DisassemblerTables.
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class RecognizableInstr {
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private:
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/// The opcode of the instruction, as used in an MCInst
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InstrUID UID;
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/// The record from the .td files corresponding to this instruction
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const Record* Rec;
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/// The OpPrefix field from the record
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uint8_t OpPrefix;
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/// The OpMap field from the record
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uint8_t OpMap;
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/// The opcode field from the record; this is the opcode used in the Intel
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/// encoding and therefore distinct from the UID
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uint8_t Opcode;
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/// The form field from the record
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uint8_t Form;
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// The encoding field from the record
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uint8_t Encoding;
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/// The OpSize field from the record
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uint8_t OpSize;
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/// The AdSize field from the record
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uint8_t AdSize;
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/// The hasREX_WPrefix field from the record
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bool HasREX_WPrefix;
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/// The hasVEX_4V field from the record
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bool HasVEX_4V;
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/// The HasVEX_WPrefix field from the record
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bool HasVEX_W;
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/// The IgnoresVEX_W field from the record
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bool IgnoresVEX_W;
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/// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
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bool HasVEX_LPrefix;
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/// The ignoreVEX_L field from the record
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bool IgnoresVEX_L;
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/// The hasEVEX_L2Prefix field from the record
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bool HasEVEX_L2Prefix;
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/// The hasEVEX_K field from the record
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bool HasEVEX_K;
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/// The hasEVEX_KZ field from the record
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bool HasEVEX_KZ;
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/// The hasEVEX_B field from the record
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bool HasEVEX_B;
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/// Indicates that the instruction uses the L and L' fields for RC.
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bool EncodeRC;
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/// The isCodeGenOnly field from the record
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bool IsCodeGenOnly;
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/// The ForceDisassemble field from the record
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bool ForceDisassemble;
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// The CD8_Scale field from the record
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uint8_t CD8_Scale;
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// Whether the instruction has the predicate "In64BitMode"
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bool Is64Bit;
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// Whether the instruction has the predicate "In32BitMode"
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bool Is32Bit;
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/// The instruction name as listed in the tables
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std::string Name;
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/// Indicates whether the instruction should be emitted into the decode
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/// tables; regardless, it will be emitted into the instruction info table
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bool ShouldBeEmitted;
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/// The operands of the instruction, as listed in the CodeGenInstruction.
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/// They are not one-to-one with operands listed in the MCInst; for example,
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/// memory operands expand to 5 operands in the MCInst
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const std::vector<CGIOperandList::OperandInfo>* Operands;
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/// The description of the instruction that is emitted into the instruction
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/// info table
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InstructionSpecifier* Spec;
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/// insnContext - Returns the primary context in which the instruction is
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/// valid.
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///
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/// @return - The context in which the instruction is valid.
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InstructionContext insnContext() const;
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/// typeFromString - Translates an operand type from the string provided in
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/// the LLVM tables to an OperandType for use in the operand specifier.
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///
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/// @param s - The string, as extracted by calling Rec->getName()
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/// on a CodeGenInstruction::OperandInfo.
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/// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
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/// prefix. If it does, 32-bit register operands stay
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/// 32-bit regardless of the operand size.
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/// @param OpSize Indicates the operand size of the instruction.
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/// If register size does not match OpSize, then
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/// register sizes keep their size.
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/// @return - The operand's type.
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static OperandType typeFromString(const std::string& s,
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bool hasREX_WPrefix, uint8_t OpSize);
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/// immediateEncodingFromString - Translates an immediate encoding from the
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/// string provided in the LLVM tables to an OperandEncoding for use in
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/// the operand specifier.
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///
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/// @param s - See typeFromString().
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/// @param OpSize - Indicates whether this is an OpSize16 instruction.
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/// If it is not, then 16-bit immediate operands stay 16-bit.
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/// @return - The operand's encoding.
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static OperandEncoding immediateEncodingFromString(const std::string &s,
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uint8_t OpSize);
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/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
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/// handles operands that are in the REG field of the ModR/M byte.
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static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
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uint8_t OpSize);
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/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
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/// handles operands that are in the REG field of the ModR/M byte.
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static OperandEncoding roRegisterEncodingFromString(const std::string &s,
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uint8_t OpSize);
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static OperandEncoding memoryEncodingFromString(const std::string &s,
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uint8_t OpSize);
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static OperandEncoding relocationEncodingFromString(const std::string &s,
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uint8_t OpSize);
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static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
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uint8_t OpSize);
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static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
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uint8_t OpSize);
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static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
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uint8_t OpSize);
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/// Adjust the encoding type for an operand based on the instruction.
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void adjustOperandEncoding(OperandEncoding &encoding);
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/// handleOperand - Converts a single operand from the LLVM table format to
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/// the emitted table format, handling any duplicate operands it encounters
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/// and then one non-duplicate.
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///
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/// @param optional - Determines whether to assert that the
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/// operand exists.
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/// @param operandIndex - The index into the generated operand table.
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/// Incremented by this function one or more
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/// times to reflect possible duplicate
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/// operands).
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/// @param physicalOperandIndex - The index of the current operand into the
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/// set of non-duplicate ('physical') operands.
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/// Incremented by this function once.
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/// @param numPhysicalOperands - The number of non-duplicate operands in the
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/// instructions.
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/// @param operandMapping - The operand mapping, which has an entry for
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/// each operand that indicates whether it is a
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/// duplicate, and of what.
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void handleOperand(bool optional,
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unsigned &operandIndex,
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unsigned &physicalOperandIndex,
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unsigned numPhysicalOperands,
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const unsigned *operandMapping,
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OperandEncoding (*encodingFromString)
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(const std::string&,
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uint8_t OpSize));
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/// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
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/// filters out many instructions, at various points in decoding we
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/// determine that the instruction should not actually be decodable. In
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/// particular, MMX MOV instructions aren't emitted, but they're only
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/// identified during operand parsing.
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///
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/// @return - true if at this point we believe the instruction should be
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/// emitted; false if not. This will return false if filter() returns false
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/// once emitInstructionSpecifier() has been called.
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bool shouldBeEmitted() const {
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return ShouldBeEmitted;
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}
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/// emitInstructionSpecifier - Loads the instruction specifier for the current
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/// instruction into a DisassemblerTables.
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///
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void emitInstructionSpecifier();
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/// emitDecodePath - Populates the proper fields in the decode tables
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/// corresponding to the decode paths for this instruction.
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///
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/// \param tables The DisassemblerTables to populate with the decode
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/// decode information for the current instruction.
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void emitDecodePath(DisassemblerTables &tables) const;
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/// Constructor - Initializes a RecognizableInstr with the appropriate fields
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/// from a CodeGenInstruction.
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///
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/// \param tables The DisassemblerTables that the specifier will be added to.
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/// \param insn The CodeGenInstruction to extract information from.
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/// \param uid The unique ID of the current instruction.
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RecognizableInstr(DisassemblerTables &tables,
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const CodeGenInstruction &insn,
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InstrUID uid);
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public:
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/// processInstr - Accepts a CodeGenInstruction and loads decode information
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/// for it into a DisassemblerTables if appropriate.
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///
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/// \param tables The DiassemblerTables to be populated with decode
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/// information.
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/// \param insn The CodeGenInstruction to be used as a source for this
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/// information.
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/// \param uid The unique ID of the instruction.
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static void processInstr(DisassemblerTables &tables,
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const CodeGenInstruction &insn,
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InstrUID uid);
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};
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} // namespace X86Disassembler
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} // namespace llvm
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#endif
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