Evan Cheng c142755cec Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past. ... llvm-svn: 76558		2009-07-21 09:15:00 +00:00
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Alpha	Make promotion in operation legalization for SETCC work correctly.	2009-07-17 05:16:04 +00:00
ARM	Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.	2009-07-21 00:31:12 +00:00
CBackend
CellSPU
CPP
Generic	remove tests for removed intrinsics.	2009-07-12 21:30:06 +00:00
IA64
Mips
MSP430
PIC16	Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes	2009-07-20 22:02:59 +00:00
PowerPC	Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.	2009-07-16 20:58:34 +00:00
SPARC
SystemZ	Enable cross register class coalescing.	2009-07-18 02:10:10 +00:00
Thumb	remove a very large testcase for now.	2009-07-21 06:28:36 +00:00
Thumb2	Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.	2009-07-21 00:31:12 +00:00
X86	Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.	2009-07-21 09:15:00 +00:00
XCore	Combine an unaligned store of unaligned load into a memmove.	2009-07-16 12:50:48 +00:00