Ahmed Bougacha 88111b0889 Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores." ... r223862 tried to also combine base-updating load/stores. r224198 reverted it, as "it created a regression on the test-suite on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order in which the words are shown." Reapply, with a fix to ignore non-normal load/stores. Truncstores are handled elsewhere (you can actually write a pattern for those, whereas for postinc loads you can't, since they return two values), but it should be possible to also combine extloads base updates, by checking that the memory (rather than result) type is of the same size as the addend. Original commit message: We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). Differential Revision: http://reviews.llvm.org/D6585 llvm-svn: 224203		2014-12-13 23:22:12 +00:00
..
2012-06-15-lsr-noaddrmode.ll	ARM & AArch64: make use of common cmpxchg idioms after expansion	2014-05-30 10:09:59 +00:00
ivchain-ARM.ll	Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."	2014-12-13 23:22:12 +00:00
lit.local.cfg	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00