mirror of
https://github.com/RPCS3/llvm-mirror.git
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8861d34661
- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses - Add comparison selection for i64 - Add zext selection for i32 -> i64 - Add shl/shr/sha support for i64 llvm-svn: 128153
637 lines
27 KiB
TableGen
637 lines
27 KiB
TableGen
//===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PTX instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "PTXInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Code Generation Predicates
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//===----------------------------------------------------------------------===//
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// Addressing
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def Use32BitAddresses : Predicate<"!getSubtarget().use64BitAddresses()">;
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def Use64BitAddresses : Predicate<"getSubtarget().use64BitAddresses()">;
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// Shader Model Support
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def SupportsSM13 : Predicate<"getSubtarget().supportsSM13()">;
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def DoesNotSupportSM13 : Predicate<"!getSubtarget().supportsSM13()">;
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def SupportsSM20 : Predicate<"getSubtarget().supportsSM20()">;
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def DoesNotSupportSM20 : Predicate<"!getSubtarget().supportsSM20()">;
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// PTX Version Support
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def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
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def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
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def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
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def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::GLOBAL;
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return false;
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}]>;
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def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::CONSTANT;
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return false;
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}]>;
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def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::LOCAL;
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return false;
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}]>;
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def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::PARAMETER;
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return false;
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}]>;
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def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::SHARED;
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return false;
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}]>;
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def store_global
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::GLOBAL;
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return false;
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}]>;
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def store_local
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::LOCAL;
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return false;
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}]>;
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def store_parameter
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::PARAMETER;
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return false;
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}]>;
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def store_shared
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::SHARED;
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return false;
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}]>;
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// Addressing modes.
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def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
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def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
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def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
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def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
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def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
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def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
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// Address operands
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def MEMri32 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops RRegu32, i32imm);
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}
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def MEMri64 : Operand<i64> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops RRegu64, i64imm);
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}
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def MEMii32 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops i32imm, i32imm);
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}
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def MEMii64 : Operand<i64> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops i64imm, i64imm);
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}
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// The operand here does not correspond to an actual address, so we
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// can use i32 in 64-bit address modes.
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def MEMpi : Operand<i32> {
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let PrintMethod = "printParamOperand";
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let MIOperandInfo = (ops i32imm);
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}
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// Branch & call targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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//===----------------------------------------------------------------------===//
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// PTX Specific Node Definitions
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//===----------------------------------------------------------------------===//
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// PTX allow generic 3-reg shifts like shl r0, r1, r2
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def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
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def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
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def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
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def PTXexit
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: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
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def PTXret
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: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
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def PTXcopyaddress
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: SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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//===- Floating-Point Instructions - 3 Operand Form -----------------------===//
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multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
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def rr32 : InstPTX<(outs RRegf32:$d),
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(ins RRegf32:$a, RRegf32:$b),
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!strconcat(opcstr, ".f32\t$d, $a, $b"),
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[(set RRegf32:$d, (opnode RRegf32:$a, RRegf32:$b))]>;
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def ri32 : InstPTX<(outs RRegf32:$d),
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(ins RRegf32:$a, f32imm:$b),
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!strconcat(opcstr, ".f32\t$d, $a, $b"),
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[(set RRegf32:$d, (opnode RRegf32:$a, fpimm:$b))]>;
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def rr64 : InstPTX<(outs RRegf64:$d),
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(ins RRegf64:$a, RRegf64:$b),
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!strconcat(opcstr, ".f64\t$d, $a, $b"),
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[(set RRegf64:$d, (opnode RRegf64:$a, RRegf64:$b))]>;
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def ri64 : InstPTX<(outs RRegf64:$d),
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(ins RRegf64:$a, f64imm:$b),
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!strconcat(opcstr, ".f64\t$d, $a, $b"),
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[(set RRegf64:$d, (opnode RRegf64:$a, fpimm:$b))]>;
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}
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//===- Floating-Point Instructions - 4 Operand Form -----------------------===//
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multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
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def rrr32 : InstPTX<(outs RRegf32:$d),
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(ins RRegf32:$a, RRegf32:$b, RRegf32:$c),
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!strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
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[(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
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RRegf32:$b),
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RRegf32:$c))]>;
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def rri32 : InstPTX<(outs RRegf32:$d),
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(ins RRegf32:$a, RRegf32:$b, f32imm:$c),
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!strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
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[(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
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RRegf32:$b),
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fpimm:$c))]>;
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def rrr64 : InstPTX<(outs RRegf64:$d),
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(ins RRegf64:$a, RRegf64:$b, RRegf64:$c),
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!strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
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[(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
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RRegf64:$b),
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RRegf64:$c))]>;
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def rri64 : InstPTX<(outs RRegf64:$d),
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(ins RRegf64:$a, RRegf64:$b, f64imm:$c),
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!strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
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[(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
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RRegf64:$b),
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fpimm:$c))]>;
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}
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multiclass INT3<string opcstr, SDNode opnode> {
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def rr16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, RRegu16:$b),
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!strconcat(opcstr, ".u16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
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def ri16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, i16imm:$b),
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!strconcat(opcstr, ".u16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
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def rr32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, RRegu32:$b),
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!strconcat(opcstr, ".u32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
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def ri32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, i32imm:$b),
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!strconcat(opcstr, ".u32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
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def rr64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, RRegu64:$b),
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!strconcat(opcstr, ".u64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
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def ri64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, i64imm:$b),
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!strconcat(opcstr, ".u64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
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}
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multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
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def rr16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, RRegu16:$b),
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!strconcat(opcstr, ".b16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
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def ri16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, i16imm:$b),
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!strconcat(opcstr, ".b16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
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def rr32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, RRegu32:$b),
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!strconcat(opcstr, ".b32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
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def ri32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, i32imm:$b),
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!strconcat(opcstr, ".b32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
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def rr64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, RRegu64:$b),
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!strconcat(opcstr, ".b64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
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def ri64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, i64imm:$b),
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!strconcat(opcstr, ".b64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
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}
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multiclass INT3ntnc<string opcstr, SDNode opnode> {
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def rr16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, RRegu16:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
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def rr32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, RRegu32:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
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def rr64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, RRegu64:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
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def ri16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, i16imm:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
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def ri32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, i32imm:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
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def ri64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, i64imm:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
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def ir16 : InstPTX<(outs RRegu16:$d),
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(ins i16imm:$a, RRegu16:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode imm:$a, RRegu16:$b))]>;
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def ir32 : InstPTX<(outs RRegu32:$d),
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(ins i32imm:$a, RRegu32:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
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def ir64 : InstPTX<(outs RRegu64:$d),
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(ins i64imm:$a, RRegu64:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode imm:$a, RRegu64:$b))]>;
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}
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multiclass PTX_SETP<RegisterClass RC, string regclsname, Operand immcls,
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CondCode cmp, string cmpstr> {
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def rr
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: InstPTX<(outs Preds:$d), (ins RC:$a, RC:$b),
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!strconcat("setp.", cmpstr, ".", regclsname, "\t$d, $a, $b"),
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[(set Preds:$d, (setcc RC:$a, RC:$b, cmp))]>;
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def ri
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: InstPTX<(outs Preds:$d), (ins RC:$a, immcls:$b),
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!strconcat("setp.", cmpstr, ".", regclsname, "\t$d, $a, $b"),
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[(set Preds:$d, (setcc RC:$a, imm:$b, cmp))]>;
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}
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multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
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def rr32 : InstPTX<(outs RC:$d),
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(ins MEMri32:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
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def rr64 : InstPTX<(outs RC:$d),
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(ins MEMri64:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
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def ri32 : InstPTX<(outs RC:$d),
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(ins MEMri32:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
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def ri64 : InstPTX<(outs RC:$d),
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(ins MEMri64:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
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def ii32 : InstPTX<(outs RC:$d),
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(ins MEMii32:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
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def ii64 : InstPTX<(outs RC:$d),
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(ins MEMii64:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
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}
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multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
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defm u16 : PTX_LD<opstr, ".u16", RRegu16, pat_load>;
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defm u32 : PTX_LD<opstr, ".u32", RRegu32, pat_load>;
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defm u64 : PTX_LD<opstr, ".u64", RRegu64, pat_load>;
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defm f32 : PTX_LD<opstr, ".f32", RRegf32, pat_load>;
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defm f64 : PTX_LD<opstr, ".f64", RRegf64, pat_load>;
|
|
}
|
|
|
|
multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
|
|
def rr32 : InstPTX<(outs),
|
|
(ins RC:$d, MEMri32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
|
|
def rr64 : InstPTX<(outs),
|
|
(ins RC:$d, MEMri64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
|
|
def ri32 : InstPTX<(outs),
|
|
(ins RC:$d, MEMri32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
|
|
def ri64 : InstPTX<(outs),
|
|
(ins RC:$d, MEMri64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
|
|
def ii32 : InstPTX<(outs),
|
|
(ins RC:$d, MEMii32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
|
|
def ii64 : InstPTX<(outs),
|
|
(ins RC:$d, MEMii64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
|
|
}
|
|
|
|
multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
|
|
defm u16 : PTX_ST<opstr, ".u16", RRegu16, pat_store>;
|
|
defm u32 : PTX_ST<opstr, ".u32", RRegu32, pat_store>;
|
|
defm u64 : PTX_ST<opstr, ".u64", RRegu64, pat_store>;
|
|
defm f32 : PTX_ST<opstr, ".f32", RRegf32, pat_store>;
|
|
defm f64 : PTX_ST<opstr, ".f64", RRegf64, pat_store>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
///===- Integer Arithmetic Instructions -----------------------------------===//
|
|
|
|
defm ADD : INT3<"add", add>;
|
|
defm SUB : INT3<"sub", sub>;
|
|
defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
|
|
|
|
///===- Floating-Point Arithmetic Instructions ----------------------------===//
|
|
|
|
// Standard Binary Operations
|
|
defm FADD : PTX_FLOAT_3OP<"add", fadd>;
|
|
defm FSUB : PTX_FLOAT_3OP<"sub", fsub>;
|
|
defm FMUL : PTX_FLOAT_3OP<"mul", fmul>;
|
|
|
|
// TODO: Allow user selection of rounding modes for fdiv.
|
|
// For division, we need to have f32 and f64 differently.
|
|
// For f32, we just always use .approx since it is supported on all hardware
|
|
// for PTX 1.4+, which is our minimum target.
|
|
def FDIVrr32 : InstPTX<(outs RRegf32:$d),
|
|
(ins RRegf32:$a, RRegf32:$b),
|
|
"div.approx.f32\t$d, $a, $b",
|
|
[(set RRegf32:$d, (fdiv RRegf32:$a, RRegf32:$b))]>;
|
|
def FDIVri32 : InstPTX<(outs RRegf32:$d),
|
|
(ins RRegf32:$a, f32imm:$b),
|
|
"div.approx.f32\t$d, $a, $b",
|
|
[(set RRegf32:$d, (fdiv RRegf32:$a, fpimm:$b))]>;
|
|
|
|
// For f64, we must specify a rounding for sm 1.3+ but *not* for sm 1.0.
|
|
def FDIVrr64SM13 : InstPTX<(outs RRegf64:$d),
|
|
(ins RRegf64:$a, RRegf64:$b),
|
|
"div.rn.f64\t$d, $a, $b",
|
|
[(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
|
|
Requires<[SupportsSM13]>;
|
|
def FDIVri64SM13 : InstPTX<(outs RRegf64:$d),
|
|
(ins RRegf64:$a, f64imm:$b),
|
|
"div.rn.f64\t$d, $a, $b",
|
|
[(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
|
|
Requires<[SupportsSM13]>;
|
|
def FDIVrr64SM10 : InstPTX<(outs RRegf64:$d),
|
|
(ins RRegf64:$a, RRegf64:$b),
|
|
"div.f64\t$d, $a, $b",
|
|
[(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
|
|
Requires<[DoesNotSupportSM13]>;
|
|
def FDIVri64SM10 : InstPTX<(outs RRegf64:$d),
|
|
(ins RRegf64:$a, f64imm:$b),
|
|
"div.f64\t$d, $a, $b",
|
|
[(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
|
|
Requires<[DoesNotSupportSM13]>;
|
|
|
|
|
|
|
|
// Multi-operation hybrid instructions
|
|
|
|
// The selection of mad/fma is tricky. In some cases, they are the *same*
|
|
// instruction, but in other cases we may prefer one or the other. Also,
|
|
// different PTX versions differ on whether rounding mode flags are required.
|
|
// In the short term, mad is supported on all PTX versions and we use a
|
|
// default rounding mode no matter what shader model or PTX version.
|
|
// TODO: Allow the rounding mode to be selectable through llc.
|
|
defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13]>;
|
|
defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13]>;
|
|
|
|
///===- Floating-Point Intrinsic Instructions -----------------------------===//
|
|
|
|
def FSQRT32 : InstPTX<(outs RRegf32:$d),
|
|
(ins RRegf32:$a),
|
|
"sqrt.rn.f32\t$d, $a",
|
|
[(set RRegf32:$d, (fsqrt RRegf32:$a))]>;
|
|
|
|
def FSQRT64 : InstPTX<(outs RRegf64:$d),
|
|
(ins RRegf64:$a),
|
|
"sqrt.rn.f64\t$d, $a",
|
|
[(set RRegf64:$d, (fsqrt RRegf64:$a))]>;
|
|
|
|
def FSIN32 : InstPTX<(outs RRegf32:$d),
|
|
(ins RRegf32:$a),
|
|
"sin.approx.f32\t$d, $a",
|
|
[(set RRegf32:$d, (fsin RRegf32:$a))]>;
|
|
|
|
def FSIN64 : InstPTX<(outs RRegf64:$d),
|
|
(ins RRegf64:$a),
|
|
"sin.approx.f64\t$d, $a",
|
|
[(set RRegf64:$d, (fsin RRegf64:$a))]>;
|
|
|
|
def FCOS32 : InstPTX<(outs RRegf32:$d),
|
|
(ins RRegf32:$a),
|
|
"cos.approx.f32\t$d, $a",
|
|
[(set RRegf32:$d, (fcos RRegf32:$a))]>;
|
|
|
|
def FCOS64 : InstPTX<(outs RRegf64:$d),
|
|
(ins RRegf64:$a),
|
|
"cos.approx.f64\t$d, $a",
|
|
[(set RRegf64:$d, (fcos RRegf64:$a))]>;
|
|
|
|
|
|
///===- Comparison and Selection Instructions -----------------------------===//
|
|
|
|
defm SETPEQu32 : PTX_SETP<RRegu32, "u32", i32imm, SETEQ, "eq">;
|
|
defm SETPNEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETNE, "ne">;
|
|
defm SETPLTu32 : PTX_SETP<RRegu32, "u32", i32imm, SETULT, "lt">;
|
|
defm SETPLEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETULE, "le">;
|
|
defm SETPGTu32 : PTX_SETP<RRegu32, "u32", i32imm, SETUGT, "gt">;
|
|
defm SETPGEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETUGE, "ge">;
|
|
defm SETPEQu64 : PTX_SETP<RRegu64, "u64", i64imm, SETEQ, "eq">;
|
|
defm SETPNEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETNE, "ne">;
|
|
defm SETPLTu64 : PTX_SETP<RRegu64, "u64", i64imm, SETULT, "lt">;
|
|
defm SETPLEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETULE, "le">;
|
|
defm SETPGTu64 : PTX_SETP<RRegu64, "u64", i64imm, SETUGT, "gt">;
|
|
defm SETPGEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETUGE, "ge">;
|
|
|
|
///===- Logic and Shift Instructions --------------------------------------===//
|
|
|
|
defm SHL : INT3ntnc<"shl.b", PTXshl>;
|
|
defm SRL : INT3ntnc<"shr.u", PTXsrl>;
|
|
defm SRA : INT3ntnc<"shr.s", PTXsra>;
|
|
|
|
defm AND : PTX_LOGIC<"and", and>;
|
|
defm OR : PTX_LOGIC<"or", or>;
|
|
defm XOR : PTX_LOGIC<"xor", xor>;
|
|
|
|
///===- Data Movement and Conversion Instructions -------------------------===//
|
|
|
|
let neverHasSideEffects = 1 in {
|
|
def MOVPREDrr
|
|
: InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
|
|
def MOVU16rr
|
|
: InstPTX<(outs RRegu16:$d), (ins RRegu16:$a), "mov.u16\t$d, $a", []>;
|
|
def MOVU32rr
|
|
: InstPTX<(outs RRegu32:$d), (ins RRegu32:$a), "mov.u32\t$d, $a", []>;
|
|
def MOVU64rr
|
|
: InstPTX<(outs RRegu64:$d), (ins RRegu64:$a), "mov.u64\t$d, $a", []>;
|
|
def MOVF32rr
|
|
: InstPTX<(outs RRegf32:$d), (ins RRegf32:$a), "mov.f32\t$d, $a", []>;
|
|
def MOVF64rr
|
|
: InstPTX<(outs RRegf64:$d), (ins RRegf64:$a), "mov.f64\t$d, $a", []>;
|
|
}
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
|
|
def MOVPREDri
|
|
: InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
|
|
[(set Preds:$d, imm:$a)]>;
|
|
def MOVU16ri
|
|
: InstPTX<(outs RRegu16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
|
|
[(set RRegu16:$d, imm:$a)]>;
|
|
def MOVU32ri
|
|
: InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
|
|
[(set RRegu32:$d, imm:$a)]>;
|
|
def MOVU164ri
|
|
: InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
|
|
[(set RRegu64:$d, imm:$a)]>;
|
|
def MOVF32ri
|
|
: InstPTX<(outs RRegf32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
|
|
[(set RRegf32:$d, fpimm:$a)]>;
|
|
def MOVF64ri
|
|
: InstPTX<(outs RRegf64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
|
|
[(set RRegf64:$d, fpimm:$a)]>;
|
|
}
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
|
|
def MOVaddr32
|
|
: InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
|
|
[(set RRegu32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
|
|
def MOVaddr64
|
|
: InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
|
|
[(set RRegu64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
|
|
}
|
|
|
|
// Loads
|
|
defm LDg : PTX_LD_ALL<"ld.global", load_global>;
|
|
defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
|
|
defm LDl : PTX_LD_ALL<"ld.local", load_local>;
|
|
defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
|
|
|
|
// This is a special instruction that is manually inserted for kernel parameters
|
|
def LDpiU16 : InstPTX<(outs RRegu16:$d), (ins MEMpi:$a),
|
|
"ld.param.u16\t$d, [$a]", []>;
|
|
def LDpiU32 : InstPTX<(outs RRegu32:$d), (ins MEMpi:$a),
|
|
"ld.param.u32\t$d, [$a]", []>;
|
|
def LDpiU64 : InstPTX<(outs RRegu64:$d), (ins MEMpi:$a),
|
|
"ld.param.u64\t$d, [$a]", []>;
|
|
def LDpiF32 : InstPTX<(outs RRegf32:$d), (ins MEMpi:$a),
|
|
"ld.param.f32\t$d, [$a]", []>;
|
|
def LDpiF64 : InstPTX<(outs RRegf64:$d), (ins MEMpi:$a),
|
|
"ld.param.f64\t$d, [$a]", []>;
|
|
|
|
// Stores
|
|
defm STg : PTX_ST_ALL<"st.global", store_global>;
|
|
defm STl : PTX_ST_ALL<"st.local", store_local>;
|
|
defm STs : PTX_ST_ALL<"st.shared", store_shared>;
|
|
|
|
// defm STp : PTX_ST_ALL<"st.param", store_parameter>;
|
|
// defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
|
|
// TODO: Do something with st.param if/when it is needed.
|
|
|
|
def CVT_u32_pred
|
|
: InstPTX<(outs RRegu32:$d), (ins Preds:$a), "cvt.u32.pred\t$d, $a",
|
|
[(set RRegu32:$d, (zext Preds:$a))]>;
|
|
|
|
def CVT_u64_u32
|
|
: InstPTX<(outs RRegu64:$d), (ins RRegu32:$a), "cvt.u64.u32\t$d, $a",
|
|
[(set RRegu64:$d, (zext RRegu32:$a))]>;
|
|
|
|
///===- Control Flow Instructions -----------------------------------------===//
|
|
|
|
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
|
|
def BRAd
|
|
: InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
|
|
}
|
|
|
|
let isBranch = 1, isTerminator = 1 in {
|
|
// FIXME: should be able to write a pattern for brcond, but can't use
|
|
// a two-value operand where a dag node expects two operands. :(
|
|
// NOTE: ARM & PowerPC backend also report the same problem
|
|
def BRAdp
|
|
: InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
|
|
[/*(brcond bb:$d, Preds:$p, i32imm:$c)*/]>;
|
|
}
|
|
|
|
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
|
|
def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
|
|
def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
|
|
}
|
|
|
|
///===- Intrinsic Instructions --------------------------------------------===//
|
|
|
|
include "PTXIntrinsicInstrInfo.td"
|