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llvm-mirror/test/MC/Mips/macro-divu-bad.s
Daniel Sanders 05de5fe69f [mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler.
Summary:

Patch by Scott Egerton

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11675

llvm-svn: 246763
2015-09-03 12:31:22 +00:00

19 lines
633 B
ArmAsm

# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
.text
divu $25, $11
# R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
divu $25, $0
# NOT-R6: :[[@LINE-1]]:3: warning: division by zero
divu $0,$0
# NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero