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llvm-mirror/lib/Target/Hexagon/Disassembler
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Brian Cain 8a9cdbd9d8 [Hexagon] v67+ HVX register pairs should support either direction 
Assembler now permits pairs like 'v0:1', which are encoded
differently from the odd-first pairs like 'v1:0'.

The compiler will require more work to leverage these new register
pairs.
2020-02-14 12:43:43 -06:00
..
CMakeLists.txt
HexagonDisassembler.cpp [Hexagon] v67+ HVX register pairs should support either direction 2020-02-14 12:43:43 -06:00
LLVMBuild.txt