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https://github.com/RPCS3/llvm-mirror.git
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089a27de75
When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
260 lines
7.3 KiB
LLVM
260 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
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declare i8 @llvm.fshl.i8(i8, i8, i8)
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declare i16 @llvm.fshl.i16(i16, i16, i16)
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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declare i8 @llvm.fshr.i8(i8, i8, i8)
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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; General case - all operands can be variables.
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define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: fshl_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi. 5, 5, 31
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; CHECK-NEXT: subfic 6, 5, 32
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; CHECK-NEXT: slw 5, 3, 5
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; CHECK-NEXT: srw 4, 4, 6
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; CHECK-NEXT: or 4, 5, 4
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; CHECK-NEXT: isel 3, 3, 4, 2
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
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ret i32 %f
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}
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; Verify that weird types are minimally supported.
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declare i37 @llvm.fshl.i37(i37, i37, i37)
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define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
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; CHECK-LABEL: fshl_i37:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis 6, -8857
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; CHECK-NEXT: clrldi 5, 5, 27
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; CHECK-NEXT: ori 6, 6, 51366
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; CHECK-NEXT: clrldi 4, 4, 27
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; CHECK-NEXT: sldi 6, 6, 32
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; CHECK-NEXT: oris 6, 6, 3542
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; CHECK-NEXT: ori 6, 6, 31883
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; CHECK-NEXT: mulhdu 6, 5, 6
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; CHECK-NEXT: rldicl 6, 6, 59, 5
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; CHECK-NEXT: mulli 6, 6, 37
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; CHECK-NEXT: subf. 5, 6, 5
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; CHECK-NEXT: subfic 6, 5, 37
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; CHECK-NEXT: sld 5, 3, 5
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; CHECK-NEXT: srd 4, 4, 6
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; CHECK-NEXT: or 4, 5, 4
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; CHECK-NEXT: isel 3, 3, 4, 2
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; CHECK-NEXT: blr
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%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
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ret i37 %f
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}
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; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
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declare i7 @llvm.fshl.i7(i7, i7, i7)
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define i7 @fshl_i7_const_fold() {
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; CHECK-LABEL: fshl_i7_const_fold:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 3, 67
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; CHECK-NEXT: blr
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%f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
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ret i7 %f
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}
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; With constant shift amount, this is rotate + insert (missing extended mnemonics).
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define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_i32_const_shift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31
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; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
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ret i32 %f
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}
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; Check modulo math on shift amount.
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define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_i32_const_overshift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31
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; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
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ret i32 %f
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}
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; 64-bit should also work.
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define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
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; CHECK-LABEL: fshl_i64_const_overshift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rotldi 4, 4, 41
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; CHECK-NEXT: rldimi 4, 3, 41, 0
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
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ret i64 %f
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}
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; This should work without any node-specific logic.
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define i8 @fshl_i8_const_fold() {
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; CHECK-LABEL: fshl_i8_const_fold:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 3, 128
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; CHECK-NEXT: blr
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%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
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ret i8 %f
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}
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; Repeat everything for funnel shift right.
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; General case - all operands can be variables.
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define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: fshr_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi. 5, 5, 31
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; CHECK-NEXT: subfic 6, 5, 32
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; CHECK-NEXT: srw 5, 4, 5
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; CHECK-NEXT: slw 3, 3, 6
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; CHECK-NEXT: or 3, 3, 5
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; CHECK-NEXT: isel 3, 4, 3, 2
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
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ret i32 %f
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}
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; Verify that weird types are minimally supported.
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declare i37 @llvm.fshr.i37(i37, i37, i37)
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define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
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; CHECK-LABEL: fshr_i37:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis 6, -8857
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; CHECK-NEXT: clrldi 5, 5, 27
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; CHECK-NEXT: ori 6, 6, 51366
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; CHECK-NEXT: sldi 6, 6, 32
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; CHECK-NEXT: oris 6, 6, 3542
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; CHECK-NEXT: ori 6, 6, 31883
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; CHECK-NEXT: mulhdu 6, 5, 6
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; CHECK-NEXT: rldicl 6, 6, 59, 5
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; CHECK-NEXT: mulli 6, 6, 37
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; CHECK-NEXT: subf. 5, 6, 5
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; CHECK-NEXT: clrldi 6, 4, 27
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; CHECK-NEXT: subfic 7, 5, 37
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; CHECK-NEXT: srd 5, 6, 5
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; CHECK-NEXT: sld 3, 3, 7
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; CHECK-NEXT: or 3, 3, 5
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; CHECK-NEXT: isel 3, 4, 3, 2
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; CHECK-NEXT: blr
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%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
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ret i37 %f
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}
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; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
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declare i7 @llvm.fshr.i7(i7, i7, i7)
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define i7 @fshr_i7_const_fold() {
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; CHECK-LABEL: fshr_i7_const_fold:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 3, 31
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; CHECK-NEXT: blr
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%f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
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ret i7 %f
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}
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; With constant shift amount, this is rotate + insert (missing extended mnemonics).
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define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
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; CHECK-LABEL: fshr_i32_const_shift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31
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; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
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ret i32 %f
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}
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; Check modulo math on shift amount. 41-32=9.
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define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
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; CHECK-LABEL: fshr_i32_const_overshift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31
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; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
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ret i32 %f
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}
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; 64-bit should also work. 105-64 = 41.
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define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
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; CHECK-LABEL: fshr_i64_const_overshift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rotldi 4, 4, 23
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; CHECK-NEXT: rldimi 4, 3, 23, 0
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
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ret i64 %f
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}
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; This should work without any node-specific logic.
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define i8 @fshr_i8_const_fold() {
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; CHECK-LABEL: fshr_i8_const_fold:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 3, 254
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; CHECK-NEXT: blr
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%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
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ret i8 %f
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}
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define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_i32_shift_by_bitwidth:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 32)
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ret i32 %f
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}
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define i32 @fshr_i32_shift_by_bitwidth(i32 %x, i32 %y) {
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; CHECK-LABEL: fshr_i32_shift_by_bitwidth:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 32)
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ret i32 %f
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}
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define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: fshl_v4i32_shift_by_bitwidth:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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define <4 x i32> @fshr_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: fshr_v4i32_shift_by_bitwidth:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmr 2, 3
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; CHECK-NEXT: blr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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