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46 lines
1.8 KiB
ArmAsm
46 lines
1.8 KiB
ArmAsm
@ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=thumbv6 -show-encoding 2>&1 < %s | FileCheck %s --check-prefix=CHECK-V6M
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.syntax unified
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.globl _func
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@ Check that the assembler can handle the documented syntax from the ARM ARM.
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@ These tests test instruction encodings specific to ARMv7m.
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@------------------------------------------------------------------------------
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@ MRS
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@------------------------------------------------------------------------------
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mrs r0, basepri
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mrs r0, basepri_max
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mrs r0, faultmask
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@ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80]
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@ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80]
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@ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80]
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@------------------------------------------------------------------------------
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@ MSR
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@------------------------------------------------------------------------------
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msr basepri, r0
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msr basepri_max, r0
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msr faultmask, r0
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@ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88]
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@ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88]
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@ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88]
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@ CHECK-V6M: error: invalid operand for instruction
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@ CHECK-V6M-NEXT: mrs r0, basepri
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@ CHECK-V6M: error: invalid operand for instruction
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@ CHECK-V6M-NEXT: mrs r0, basepri_max
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@ CHECK-V6M: error: invalid operand for instruction
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@ CHECK-V6M-NEXT: mrs r0, faultmask
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@ CHECK-V6M: error: invalid operand for instruction
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@ CHECK-V6M-NEXT: msr basepri, r0
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@ CHECK-V6M: error: invalid operand for instruction
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@ CHECK-V6M-NEXT: msr basepri_max, r0
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@ CHECK-V6M: error: invalid operand for instruction
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@ CHECK-V6M-NEXT: msr faultmask, r0
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