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llvm-mirror/test/CodeGen/X86/v-binop-widen2.ll
Andrew Trick e3e67d4a0a Enable MI Sched for x86.
This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.

Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.

On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.

Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.

The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.

Unit tests are updated so they don't depend on SD scheduling heuristics.

llvm-svn: 192750
2013-10-15 23:33:07 +00:00

48 lines
1.4 KiB
LLVM

; RUN: llc -march=x86 -mcpu=generic -mattr=+sse < %s | FileCheck %s
; RUN: llc -march=x86 -mcpu=atom -mattr=+sse < %s | FileCheck -check-prefix=ATOM %s
%vec = type <6 x float>
; CHECK: divps
; CHECK: divss
; CHECK: divss
; Scheduler causes a different instruction order to be produced on Intel Atom
; ATOM: divps
; ATOM: divss
; ATOM: divss
define %vec @vecdiv( %vec %p1, %vec %p2)
{
%result = fdiv %vec %p1, %p2
ret %vec %result
}
@a = constant %vec < float 2.0, float 4.0, float 8.0, float 16.0, float 32.0, float 64.0 >
@b = constant %vec < float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0 >
; Expected result: < 1.0, 2.0, 4.0, ..., 2.0^(n-1) >
; main() returns 0 if the result is expected and 1 otherwise
; to execute, use llvm-as < %s | lli
define i32 @main() nounwind {
entry:
%avec = load %vec* @a
%bvec = load %vec* @b
%res = call %vec @vecdiv(%vec %avec, %vec %bvec)
br label %loop
loop:
%idx = phi i32 [0, %entry], [%nextInd, %looptail]
%expected = phi float [1.0, %entry], [%nextExpected, %looptail]
%elem = extractelement %vec %res, i32 %idx
%expcmp = fcmp oeq float %elem, %expected
br i1 %expcmp, label %looptail, label %return
looptail:
%nextExpected = fmul float %expected, 2.0
%nextInd = add i32 %idx, 1
%cmp = icmp slt i32 %nextInd, 6
br i1 %cmp, label %loop, label %return
return:
%retval = phi i32 [0, %looptail], [1, %loop]
ret i32 %retval
}