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https://github.com/RPCS3/llvm-mirror.git
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29ebc2d39f
Summary: DataLayout keeps the string used for its creation. As a side effect it is no longer needed in the Module. This is "almost" NFC, the string is no longer canonicalized, you can't rely on two "equals" DataLayout having the same string returned by getStringRepresentation(). Get rid of DataLayoutPass: the DataLayout is in the Module The DataLayout is "per-module", let's enforce this by not duplicating it more than necessary. One more step toward non-optionality of the DataLayout in the module. Make DataLayout Non-Optional in the Module Module->getDataLayout() will never returns nullptr anymore. Reviewers: echristo Subscribers: resistor, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D7992 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231270
200 lines
6.2 KiB
LLVM
200 lines
6.2 KiB
LLVM
; RUN: opt -S -instcombine < %s | FileCheck %s
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; return mul(zext x, zext y) > MAX
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define i32 @pr4917_1(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4917_1(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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; CHECK-NOT: zext i32
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%mul64 = mul i64 %l, %r
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
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%overflow = icmp ugt i64 %mul64, 4294967295
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; CHECK: extractvalue { i32, i1 } [[MUL]], 1
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%retval = zext i1 %overflow to i32
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ret i32 %retval
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}
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; return mul(zext x, zext y) >= MAX+1
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define i32 @pr4917_1a(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4917_1a(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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; CHECK-NOT: zext i32
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%mul64 = mul i64 %l, %r
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
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%overflow = icmp uge i64 %mul64, 4294967296
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; CHECK: extractvalue { i32, i1 } [[MUL]], 1
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%retval = zext i1 %overflow to i32
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ret i32 %retval
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}
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; mul(zext x, zext y) > MAX
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; mul(x, y) is used
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define i32 @pr4917_2(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4917_2(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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; CHECK-NOT: zext i32
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%mul64 = mul i64 %l, %r
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
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%overflow = icmp ugt i64 %mul64, 4294967295
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; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
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%mul32 = trunc i64 %mul64 to i32
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; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
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%retval = select i1 %overflow, i32 %mul32, i32 111
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; CHECK: select i1 [[OVFL]], i32 [[VAL]]
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ret i32 %retval
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}
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; return mul(zext x, zext y) > MAX
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; mul is used in non-truncate
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define i64 @pr4917_3(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4917_3(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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%mul64 = mul i64 %l, %r
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; CHECK-NOT: umul.with.overflow.i32
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%overflow = icmp ugt i64 %mul64, 4294967295
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%retval = select i1 %overflow, i64 %mul64, i64 111
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ret i64 %retval
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}
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; return mul(zext x, zext y) <= MAX
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define i32 @pr4917_4(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4917_4(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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; CHECK-NOT: zext i32
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%mul64 = mul i64 %l, %r
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
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%overflow = icmp ule i64 %mul64, 4294967295
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; CHECK: extractvalue { i32, i1 } [[MUL]], 1
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; CHECK: xor
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%retval = zext i1 %overflow to i32
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ret i32 %retval
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}
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; return mul(zext x, zext y) < MAX+1
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define i32 @pr4917_4a(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4917_4a(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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; CHECK-NOT: zext i32
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%mul64 = mul i64 %l, %r
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
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%overflow = icmp ult i64 %mul64, 4294967296
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; CHECK: extractvalue { i32, i1 } [[MUL]], 1
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; CHECK: xor
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%retval = zext i1 %overflow to i32
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ret i32 %retval
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}
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; operands of mul are of different size
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define i32 @pr4917_5(i32 %x, i8 %y) nounwind {
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; CHECK-LABEL: @pr4917_5(
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entry:
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%l = zext i32 %x to i64
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%r = zext i8 %y to i64
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; CHECK: [[Y:%.*]] = zext i8 %y to i32
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%mul64 = mul i64 %l, %r
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%overflow = icmp ugt i64 %mul64, 4294967295
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%mul32 = trunc i64 %mul64 to i32
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 [[Y]])
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; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
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; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
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%retval = select i1 %overflow, i32 %mul32, i32 111
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; CHECK: select i1 [[OVFL]], i32 [[VAL]]
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ret i32 %retval
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}
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; mul(zext x, zext y) != zext trunc mul
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define i32 @pr4918_1(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4918_1(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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%mul64 = mul i64 %l, %r
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
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%part32 = trunc i64 %mul64 to i32
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%part64 = zext i32 %part32 to i64
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%overflow = icmp ne i64 %mul64, %part64
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; CHECK: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL:%.*]], 1
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%retval = zext i1 %overflow to i32
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ret i32 %retval
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}
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; mul(zext x, zext y) == zext trunc mul
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define i32 @pr4918_2(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4918_2(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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%mul64 = mul i64 %l, %r
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
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%part32 = trunc i64 %mul64 to i32
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%part64 = zext i32 %part32 to i64
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%overflow = icmp eq i64 %mul64, %part64
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; CHECK: extractvalue { i32, i1 } [[MUL]]
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%retval = zext i1 %overflow to i32
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; CHECK: xor
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ret i32 %retval
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}
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; zext trunc mul != mul(zext x, zext y)
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define i32 @pr4918_3(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @pr4918_3(
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entry:
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%l = zext i32 %x to i64
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%r = zext i32 %y to i64
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%mul64 = mul i64 %l, %r
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; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
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%part32 = trunc i64 %mul64 to i32
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%part64 = zext i32 %part32 to i64
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%overflow = icmp ne i64 %part64, %mul64
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; CHECK: extractvalue { i32, i1 } [[MUL]], 1
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%retval = zext i1 %overflow to i32
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ret i32 %retval
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}
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define <4 x i32> @pr20113(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: @pr20113
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; CHECK-NOT: mul.with.overflow
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; CHECK: ret
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%vmovl.i.i726 = zext <4 x i16> %a to <4 x i32>
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%vmovl.i.i712 = zext <4 x i16> %b to <4 x i32>
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%mul.i703 = mul <4 x i32> %vmovl.i.i712, %vmovl.i.i726
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%tmp = icmp sge <4 x i32> %mul.i703, zeroinitializer
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%vcgez.i = sext <4 x i1> %tmp to <4 x i32>
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ret <4 x i32> %vcgez.i
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}
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; The last test needs this weird datalayout.
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target datalayout = "i32:8:8"
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; Without it, InstCombine will align the pointed on 4 Bytes
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; The KnownBitsZero that result from the alignment allows to
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; turn:
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; and i32 %mul, 255
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; to:
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; and i32 %mul, 252
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; The mask is no longer in the form 2^n-1 and this prevents the transformation.
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@pr21445_data = external global i32
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define i1 @pr21445(i8 %a) {
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; CHECK-LABEL: @pr21445(
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; CHECK-NEXT: %[[umul:.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 ptrtoint (i32* @pr21445_data to i8))
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; CHECK-NEXT: %[[cmp:.*]] = extractvalue { i8, i1 } %[[umul]], 1
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; CHECK-NEXT: ret i1 %[[cmp]]
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%ext = zext i8 %a to i32
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%mul = mul i32 %ext, zext (i8 ptrtoint (i32* @pr21445_data to i8) to i32)
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%and = and i32 %mul, 255
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%cmp = icmp ne i32 %mul, %and
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ret i1 %cmp
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}
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