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288 lines
12 KiB
TableGen
288 lines
12 KiB
TableGen
//===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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// Address operands
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def op_addr_mode1 : Operand<iPTR> {
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let PrintMethod = "printAddrMode1";
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let NumMIOperands = 3;
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let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
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}
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def memri : Operand<iPTR> {
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let PrintMethod = "printMemRegImm";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops i32imm, ptr_rc);
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}
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// Define ARM specific addressing mode.
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//Addressing Mode 1: data processing operands
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def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
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[]>;
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//register plus/minus 12 bit offset
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def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
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//register plus scaled register
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//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
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let Namespace = "ARM";
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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def brtarget : Operand<OtherVT>;
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// Operand for printing out a condition code.
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let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i32>;
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def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
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def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
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def SDTarmfmstat : SDTypeProfile<0, 0, []>;
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def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
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def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
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def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
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def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
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def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
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def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
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def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
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def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
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def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
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def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
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def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
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def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
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def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
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def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
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def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
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def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
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let isReturn = 1 in {
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def bx: InstARM<(ops), "bx r14", [(retflag)]>;
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}
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let Defs = [R0, R1, R2, R3, R14] in {
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def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
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}
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def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
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"ldr $dst, $addr",
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[(set IntRegs:$dst, (load iaddr:$addr))]>;
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def str : InstARM<(ops IntRegs:$src, memri:$addr),
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"str $src, $addr",
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[(store IntRegs:$src, iaddr:$addr)]>;
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def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
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"mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
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def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"add $dst, $a, $b",
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[(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
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def ADCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"adcs $dst, $a, $b",
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[(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
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def ADDS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"adds $dst, $a, $b",
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[(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
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// "LEA" forms of add
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def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
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"add $dst, ${addr:arith}",
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[(set IntRegs:$dst, iaddr:$addr)]>;
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def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"sub $dst, $a, $b",
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[(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
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def SBCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"sbcs $dst, $a, $b",
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[(set IntRegs:$dst, (sube IntRegs:$a, addr_mode1:$b))]>;
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def SUBS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"subs $dst, $a, $b",
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[(set IntRegs:$dst, (subc IntRegs:$a, addr_mode1:$b))]>;
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def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"and $dst, $a, $b",
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[(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
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def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"eor $dst, $a, $b",
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[(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
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def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"orr $dst, $a, $b",
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[(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
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let isTwoAddress = 1 in {
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def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
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op_addr_mode1:$true, CCOp:$cc),
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"mov$cc $dst, $true",
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[(set IntRegs:$dst, (armselect addr_mode1:$true,
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IntRegs:$false, imm:$cc))]>;
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}
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def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"mul $dst, $a, $b",
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[(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
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def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
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"b$cc $dst",
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[(armbr bb:$dst, imm:$cc)]>;
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def b : InstARM<(ops brtarget:$dst),
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"b $dst",
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[(br bb:$dst)]>;
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def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
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"cmp $a, $b",
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[(armcmp IntRegs:$a, addr_mode1:$b)]>;
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// Floating Point Compare
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def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
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"fcmps $a, $b",
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[(armcmp FPRegs:$a, FPRegs:$b)]>;
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def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
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"fcmpd $a, $b",
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[(armcmp DFPRegs:$a, DFPRegs:$b)]>;
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// Floating Point Conversion
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// We use bitconvert for moving the data between the register classes.
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// The format conversion is done with ARM specific nodes
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def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
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"fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
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def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
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"fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
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def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
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"fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
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def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
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"fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
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def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
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def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
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def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
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"fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
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def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
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"ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
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def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
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def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
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def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
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"fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
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def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
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"ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
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def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
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"fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
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def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
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"fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
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def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
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// Floating Point Arithmetic
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def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
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"fadds $dst, $a, $b",
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[(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
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def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
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"faddd $dst, $a, $b",
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[(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
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def FSUBS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
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"fsubs $dst, $a, $b",
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[(set FPRegs:$dst, (fsub FPRegs:$a, FPRegs:$b))]>;
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def FSUBD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
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"fsubd $dst, $a, $b",
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[(set DFPRegs:$dst, (fsub DFPRegs:$a, DFPRegs:$b))]>;
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def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"fnegs $dst, $src",
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[(set FPRegs:$dst, (fneg FPRegs:$src))]>;
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def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
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"fnegd $dst, $src",
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[(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
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def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
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"fmuls $dst, $a, $b",
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[(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
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def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
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"fmuld $dst, $a, $b",
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[(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>;
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// Floating Point Load
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def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
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"flds $dst, $addr",
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[(set FPRegs:$dst, (load IntRegs:$addr))]>;
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def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
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"fldd $dst, $addr",
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[(set DFPRegs:$dst, (load IntRegs:$addr))]>;
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