Simon Pilgrim c4477aac03 [CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports. ... Update shl/lshr/ashr costs based on the worst case costs from the script in D103695 - many of the 128-bit shifts (usually where integer multiplies aren't used) have similar behaviour to AVX1 so we can merge them.		2021-07-22 20:07:32 +01:00
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AArch64	[AArch64] Adjust the cost of integer sum reductions	2021-07-22 18:19:54 +01:00
AMDGPU	[AMDGPU] PHI node cost should not be counted for the size and latency.	2021-06-30 16:11:17 +03:00
ARM	[CostModel] Express cost(urem) as cost(div+mul+sub) when set to Expand.	2021-07-07 14:40:28 +01:00
PowerPC	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00
RISCV	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00
SystemZ	Revert "[NFC] remove explicit default value for strboolattr attribute in tests"	2021-05-24 19:43:40 +02:00
X86	[CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports.	2021-07-22 20:07:32 +01:00
free-intrinsics-datalayout.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
free-intrinsics-no_info.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
no_info.ll