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395 lines
15 KiB
C++
395 lines
15 KiB
C++
//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instructions to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Support/DataTypes.h"
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#include <vector>
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#include <cassert>
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namespace llvm {
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class MachineInstr;
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class TargetMachine;
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class Value;
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class Type;
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class Instruction;
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class Constant;
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class Function;
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class MachineCodeForInstruction;
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class TargetRegisterClass;
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class LiveVariables;
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//---------------------------------------------------------------------------
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// Data types used to define information about a single machine instruction
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//---------------------------------------------------------------------------
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typedef short MachineOpCode;
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typedef unsigned InstrSchedClass;
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//---------------------------------------------------------------------------
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// struct TargetInstrDescriptor:
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// Predefined information about each machine instruction.
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// Designed to initialized statically.
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//
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const unsigned M_BRANCH_FLAG = 1 << 0;
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const unsigned M_CALL_FLAG = 1 << 1;
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const unsigned M_RET_FLAG = 1 << 2;
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const unsigned M_BARRIER_FLAG = 1 << 3;
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const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
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const unsigned M_LOAD_FLAG = 1 << 5;
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const unsigned M_STORE_FLAG = 1 << 6;
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// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
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// changed into a 3-address instruction if the first two operands cannot be
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// assigned to the same register. The target must implement the
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// TargetInstrInfo::convertToThreeAddress method for this instruction.
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const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7;
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// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
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// Z), which produces the same result if Y and Z are exchanged.
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const unsigned M_COMMUTABLE = 1 << 8;
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// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
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// block? Typically this is things like return and branch instructions.
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// Various passes use this to insert code into the bottom of a basic block, but
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// before control flow occurs.
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const unsigned M_TERMINATOR_FLAG = 1 << 9;
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// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
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// insertion support when the DAG scheduler is inserting it into a machine basic
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// block.
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const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
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// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
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// operands in addition to the minimum number operands specified.
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const unsigned M_VARIABLE_OPS = 1 << 11;
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// M_PREDICATED - Set if this instruction has a predicate that controls its
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// execution.
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const unsigned M_PREDICATED = 1 << 12;
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// Machine operand flags
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// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
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// requires a callback to look up its register class.
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const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
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/// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate
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/// operand that controls an M_PREDICATED instruction.
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const unsigned M_PREDICATE_OPERAND = 1 << 1;
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namespace TOI {
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// Operand constraints: only "tied_to" for now.
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enum OperandConstraint {
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TIED_TO = 0 // Must be allocated the same register as.
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};
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}
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/// TargetOperandInfo - This holds information about one operand of a machine
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/// instruction, indicating the register class for register operands, etc.
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///
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class TargetOperandInfo {
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public:
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/// RegClass - This specifies the register class enumeration of the operand
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/// if the operand is a register. If not, this contains 0.
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unsigned short RegClass;
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unsigned short Flags;
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/// Lower 16 bits are used to specify which constraints are set. The higher 16
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/// bits are used to specify the value of constraints (4 bits each).
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unsigned int Constraints;
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/// Currently no other information.
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};
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class TargetInstrDescriptor {
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public:
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MachineOpCode Opcode; // The opcode.
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unsigned short numOperands; // Num of args (may be more if variable_ops).
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const char * Name; // Assembly language mnemonic for the opcode.
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned Flags; // flags identifying machine instr class
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unsigned TSFlags; // Target Specific Flag values
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const unsigned *ImplicitUses; // Registers implicitly read by this instr
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
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/// getOperandConstraint - Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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int getOperandConstraint(unsigned OpNum,
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TOI::OperandConstraint Constraint) const {
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assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
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"Invalid operand # of TargetInstrInfo");
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if (OpNum < numOperands &&
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(OpInfo[OpNum].Constraints & (1 << Constraint))) {
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unsigned Pos = 16 + Constraint * 4;
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return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
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}
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return -1;
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}
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/// findTiedToSrcOperand - Returns the operand that is tied to the specified
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/// dest operand. Returns -1 if there isn't one.
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int findTiedToSrcOperand(unsigned OpNum) const;
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};
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//---------------------------------------------------------------------------
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///
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/// TargetInstrInfo - Interface to description of machine instructions
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///
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class TargetInstrInfo {
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const TargetInstrDescriptor* desc; // raw array to allow static init'n
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unsigned NumOpcodes; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
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virtual ~TargetInstrInfo();
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// Invariant opcodes: All instruction sets have these as their low opcodes.
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enum {
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PHI = 0,
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INLINEASM = 1,
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LABEL = 2
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};
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unsigned getNumOpcodes() const { return NumOpcodes; }
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
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assert((unsigned)Opcode < NumOpcodes);
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return desc[Opcode];
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}
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const char *getName(MachineOpCode Opcode) const {
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return get(Opcode).Name;
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}
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int getNumOperands(MachineOpCode Opcode) const {
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return get(Opcode).numOperands;
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}
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InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
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return get(Opcode).schedClass;
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}
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const unsigned *getImplicitUses(MachineOpCode Opcode) const {
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return get(Opcode).ImplicitUses;
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}
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const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
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return get(Opcode).ImplicitDefs;
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}
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//
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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bool isReturn(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_RET_FLAG;
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}
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bool isPredicated(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_PREDICATED;
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}
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bool isCommutableInstr(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_COMMUTABLE;
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}
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bool isTerminatorInstr(unsigned Opcode) const {
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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}
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bool isBranch(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_BRANCH_FLAG;
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}
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/// isBarrier - Returns true if the specified instruction stops control flow
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/// from executing the instruction immediately following it. Examples include
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/// unconditional branches and return instructions.
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bool isBarrier(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_BARRIER_FLAG;
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}
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bool isCall(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_CALL_FLAG;
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}
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bool isLoad(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_LOAD_FLAG;
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}
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bool isStore(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_STORE_FLAG;
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}
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/// hasDelaySlot - Returns true if the specified instruction has a delay slot
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/// which must be filled by the code generator.
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bool hasDelaySlot(unsigned Opcode) const {
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return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
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}
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/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
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/// custom insertion support when the DAG scheduler is inserting it into a
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/// machine basic block.
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bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
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return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
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}
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bool hasVariableOperands(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_VARIABLE_OPS;
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}
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/// getOperandConstraint - Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
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TOI::OperandConstraint Constraint) const {
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return get(Opcode).getOperandConstraint(OpNum, Constraint);
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}
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/// Return true if the instruction is a register to register move
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/// and leave the source and dest operands in the passed parameters.
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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return 0;
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}
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into one or moretrue
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/// three-address instructions on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the last new instruction.
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///
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virtual MachineInstr *
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convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
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return 0;
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}
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/// commuteInstruction - If a target has any instructions that are commutable,
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/// but require converting to a different instruction or making non-trivial
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/// changes to commute them, this method can overloaded to do this. The
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/// default implementation of this method simply swaps the first two operands
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/// of MI and returns it.
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///
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/// If a target wants to make more aggressive changes, they can construct and
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/// return a new machine instruction. If an instruction cannot commute, it
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/// can also return null.
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
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/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with an conditional branch, it returns the 'true'
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/// destination in TBB, the 'false' destination in FBB, and a list of
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/// operands that evaluate the condition. These operands can be passed to
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/// other TargetInstrInfo methods to create new branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const {
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return true;
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}
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/// RemoveBranch - Remove the branching code at the end of the specific MBB.
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/// this is only invoked in cases where AnalyzeBranch returns success.
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virtual void RemoveBranch(MachineBasicBlock &MBB) const {
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assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
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}
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/// InsertBranch - Insert a branch into the end of the specified
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/// MachineBasicBlock. This operands to this method are the same as those
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/// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
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/// returns success and when an unconditional branch (TBB is non-null, FBB is
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/// null, Cond is empty) needs to be inserted.
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virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond) const {
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assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
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}
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/// BlockHasNoFallThrough - Return true if the specified block does not
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/// fall-through into its successor block. This is primarily used when a
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/// branch is unanalyzable. It is useful for things like unconditional
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/// indirect branches (jump tables).
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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return false;
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}
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/// ReverseBranchCondition - Reverses the branch condition of the specified
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/// condition list, returning false on success and true if it cannot be
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/// reversed.
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virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
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return true;
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}
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/// insertNoop - Insert a noop into the instruction stream at the specified
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/// point.
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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assert(0 && "Target didn't implement insertNoop!");
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abort();
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}
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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virtual const TargetRegisterClass *getPointerRegClass() const {
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assert(0 && "Target didn't implement getPointerRegClass!");
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abort();
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}
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};
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} // End llvm namespace
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#endif
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