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6f4cc7f112
Summary: This also adds testing of 32-bit V9 atomic lowering, splitting the 64-bit-only tests out into their own file. Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: hiraditya, fedor.sergeev, jfb, llvm-commits, glaubitz Tags: #llvm Differential Revision: https://reviews.llvm.org/D69352
61 lines
1.4 KiB
LLVM
61 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: test_atomic_i64
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; CHECK: ldx [%o0]
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; CHECK: membar
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; CHECK: ldx [%o1]
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; CHECK: membar
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; CHECK: membar
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; CHECK: stx {{.+}}, [%o2]
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define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
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entry:
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%0 = load atomic i64, i64* %ptr1 acquire, align 8
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%1 = load atomic i64, i64* %ptr2 acquire, align 8
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%2 = add i64 %0, %1
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store atomic i64 %2, i64* %ptr3 release, align 8
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ret i64 %2
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}
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; CHECK-LABEL: test_cmpxchg_i64
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; CHECK: mov 123, [[R:%[gilo][0-7]]]
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; CHECK: casx [%o1], %o0, [[R]]
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define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
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entry:
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%pair = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
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%b = extractvalue { i64, i1 } %pair, 0
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ret i64 %b
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}
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; CHECK-LABEL: test_swap_i64
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; CHECK: casx [%o1],
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define i64 @test_swap_i64(i64 %a, i64* %ptr) {
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entry:
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%b = atomicrmw xchg i64* %ptr, i64 42 monotonic
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ret i64 %b
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}
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; CHECK-LABEL: test_load_sub_64
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; CHECK: membar
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; CHECK: sub
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; CHECK: casx [%o0]
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; CHECK: membar
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define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
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entry:
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%0 = atomicrmw sub i64* %p, i64 %v seq_cst
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ret i64 %0
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}
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; CHECK-LABEL: test_load_max_64
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; CHECK: membar
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; CHECK: cmp
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; CHECK: movg %xcc
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; CHECK: casx [%o0]
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; CHECK: membar
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define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
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entry:
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%0 = atomicrmw max i64* %p, i64 %v seq_cst
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ret i64 %0
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}
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