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https://github.com/RPCS3/llvm-mirror.git
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32875af6e3
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
71 lines
1.4 KiB
LLVM
71 lines
1.4 KiB
LLVM
; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
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define i32 @icmp_eq_i1(i1 %a) {
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; CHECK-LABEL: icmp_eq_i1
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; CHECK: tbz w0, #0, {{LBB.+_2}}
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%1 = icmp eq i1 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i8(i8 %a) {
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; CHECK-LABEL: icmp_eq_i8
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; CHECK: uxtb [[REG:w[0-9]+]], w0
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; CHECK: cbz [[REG]], {{LBB.+_2}}
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%1 = icmp eq i8 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i16(i16 %a) {
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; CHECK-LABEL: icmp_eq_i16
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; CHECK: uxth [[REG:w[0-9]+]], w0
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; CHECK: cbz [[REG]], {{LBB.+_2}}
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%1 = icmp eq i16 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i32(i32 %a) {
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; CHECK-LABEL: icmp_eq_i32
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; CHECK: cbz w0, {{LBB.+_2}}
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%1 = icmp eq i32 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i64(i64 %a) {
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; CHECK-LABEL: icmp_eq_i64
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; CHECK: cbz x0, {{LBB.+_2}}
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%1 = icmp eq i64 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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define i32 @icmp_eq_ptr(i8* %a) {
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; CHECK-LABEL: icmp_eq_ptr
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; CHECK: cbz x0, {{LBB.+_2}}
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%1 = icmp eq i8* %a, null
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br i1 %1, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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