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https://github.com/RPCS3/llvm-mirror.git
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f7cad0a97a
Summary: If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen` will set it as true for those instructions which has no match pattern. The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by `llvm-tblgen`. But in fact, we can use `[LR]` to model the two instructions, so they should not have SideEffects. This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D71390
65 lines
2.4 KiB
LLVM
65 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; The instructions addis,addi, bl are used to calculate the address of TLS
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; thread local variables. These TLS access code sequences are generated
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; repeatedly every time the thread local variable is accessed. By communicating
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; to Machine CSE that X2 is guaranteed to have the same value within the same
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; function call (so called Caller Preserved Physical Register), the redudant
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; TLS access code sequences are cleaned up.
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%"struct.CC::TT" = type { i64, i32 }
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%class.CC = type { %struct.SS }
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%struct.SS = type { void ()* }
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@_ZN2CC2ccE = external thread_local global %"struct.CC::TT", align 8
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define noalias i8* @_ZN2CC3funEv(%class.CC* %this) nounwind {
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; CHECK-LABEL: _ZN2CC3funEv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 0, 16(1)
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; CHECK-NEXT: stdu 1, -48(1)
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; CHECK-NEXT: std 2, 24(1)
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; CHECK-NEXT: mr 30, 3
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; CHECK-NEXT: ld 12, 0(3)
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; CHECK-NEXT: mtctr 12
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; CHECK-NEXT: bctrl
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; CHECK-NEXT: ld 2, 24(1)
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; CHECK-NEXT: addis 3, 2, _ZN2CC2ccE@got@tlsgd@ha
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; CHECK-NEXT: addi 3, 3, _ZN2CC2ccE@got@tlsgd@l
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; CHECK-NEXT: bl __tls_get_addr(_ZN2CC2ccE@tlsgd)
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; CHECK-NEXT: nop
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; CHECK-NEXT: ld 4, 0(3)
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; CHECK-NEXT: cmpldi 4, 0
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; CHECK-NEXT: beq 0, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addi 4, 3, 8
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; CHECK-NEXT: mr 3, 30
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; CHECK-NEXT: bl _ZN2CC3barEPi
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB0_2: # %if.end
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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%foo = getelementptr inbounds %class.CC, %class.CC* %this, i64 0, i32 0, i32 0
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%0 = load void ()*, void ()** %foo, align 8
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tail call void %0()
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%1 = load i64, i64* getelementptr inbounds (%"struct.CC::TT", %"struct.CC::TT"* @_ZN2CC2ccE, i64 0, i32 0)
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%tobool = icmp eq i64 %1, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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tail call void @_ZN2CC3barEPi(%class.CC* nonnull %this, i32* getelementptr inbounds (%"struct.CC::TT", %"struct.CC::TT"* @_ZN2CC2ccE, i64 0, i32 1))
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br label %if.end
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if.end:
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ret i8* null
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}
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declare void @_ZN2CC3barEPi(%class.CC*, i32*)
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