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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
llvm-mirror/test/CodeGen
Fraser Cormack 94d12e2de0 [RISCV] Transform unaligned RVV vector loads/stores to aligned ones
This patch adds support for loading and storing unaligned vectors via an
equivalently-sized i8 vector type, which has support in the RVV
specification for byte-aligned access.

This offers a more optimal path for handling of unaligned fixed-length
vector accesses, which are currently scalarized. It also prevents
crashing when `LegalizeDAG` sees an unaligned scalable-vector load/store
operation.

Future work could be to investigate loading/storing via the largest
vector element type for the given alignment, in case that would be more
optimal on hardware. For instance, a 4-byte-aligned nxv2i64 vector load
could loaded as nxv4i32 instead of as nxv16i8.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D104032
2021-06-14 18:12:18 +01:00
..
AArch64 [AArch64] Improve SAD pattern 2021-06-14 15:48:51 +01:00
AMDGPU [AMDGPU][IndirectCalls] Fix register usage propagation for indirect/external calls 2021-06-12 11:59:34 +05:30
ARC
ARM [ARM][NEON] Combine base address updates for vld1Ndup intrinsics 2021-06-13 11:18:32 +02:00
AVR
BPF
Generic
Hexagon
Inputs
Lanai
M68k
Mips
MIR Implement DW_CFA_LLVM_* for Heterogeneous Debugging 2021-06-14 08:51:50 +05:30
MSP430
NVPTX
PowerPC [AIX][XCOFF] emit vector info of traceback table. 2021-06-14 11:15:22 -04:00
RISCV [RISCV] Transform unaligned RVV vector loads/stores to aligned ones 2021-06-14 18:12:18 +01:00
SPARC [SPARC] Legalize truncation and extension between fp128 and half 2021-06-13 20:05:15 +02:00
SystemZ
Thumb
Thumb2 [ARM] Introduce t2WhileLoopStartTP 2021-06-13 13:55:34 +01:00
VE
WebAssembly
WinCFGuard
WinEH
X86 [DAGCombine] reduceBuildVecToShuffle(): sort input vectors by decreasing size 2021-06-14 16:18:37 +03:00
XCore