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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
17 lines
583 B
LLVM
17 lines
583 B
LLVM
; RUN: llc < %s -mcpu=generic -march=x86 | grep add | not grep 16
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%struct.W = type { x86_fp80, x86_fp80 }
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@B = global %struct.W { x86_fp80 0xK4001A000000000000000, x86_fp80 0xK4001C000000000000000 }, align 32
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@.cpx = internal constant %struct.W { x86_fp80 0xK4001E000000000000000, x86_fp80 0xK40028000000000000000 }
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define i32 @main() nounwind {
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entry:
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tail call void (i32, ...)* @bar( i32 3, %struct.W* byval @.cpx ) nounwind
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tail call void (i32, ...)* @baz( i32 3, %struct.W* byval @B ) nounwind
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ret i32 undef
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}
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declare void @bar(i32, ...)
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declare void @baz(i32, ...)
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